{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,12]],"date-time":"2026-06-12T21:05:04Z","timestamp":1781298304825,"version":"3.54.1"},"reference-count":23,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2007]]},"DOI":"10.1109\/test.2007.4437606","type":"proceedings-article","created":{"date-parts":[[2008,1,29]],"date-time":"2008-01-29T15:41:30Z","timestamp":1201621290000},"page":"1-10","source":"Crossref","is-referenced-by-count":3,"title":["A methodology for systematic built-in self-test of phase-locked loops targeting at parametric failures"],"prefix":"10.1109","author":[{"family":"Guo Yu","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"family":"Peng Li","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"19","author":"vapnik","year":"1998","journal-title":"Statistical Learning Theory"},{"key":"22","first-page":"155","article-title":"parameter variation on chip-level","author":"schaper","year":"2005","journal-title":"IEEE Int Conf on Microelectronic Test Structures"},{"key":"17","article-title":"performance-oriented statistical parameter reduction of parameterized systems via reduced rank regression","author":"feng","year":"2006","journal-title":"Proc IEEE\/ACM Int Conf CAD"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065746"},{"key":"18","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4757-2853-8","author":"reinsel","year":"1998","journal-title":"Multivariate Reduced-Rank Regression Theory and Applications"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/SOUTHC.1996.535101"},{"key":"16","author":"morrison","year":"1976","journal-title":"Multivariate Statistical Methods"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.1999.759717"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2005.1465800"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1997.600251"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2006.229165"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1989.572629"},{"key":"3","first-page":"980","article-title":"power supply ramping for quasi-static testing of plls","author":"gyvez","year":"2004","journal-title":"IEEE proc of the International Test Conference"},{"key":"20","first-page":"201","article-title":"new paradigm of predictive mosfet and interconnect modeling for early circuit design","author":"cao","year":"2000","journal-title":"IEEE Custom Integrated Circuits Conference"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1999.805777"},{"key":"1","author":"best","year":"2003","journal-title":"Phase-Locked Loops Design Simulation and Applications"},{"key":"10","article-title":"verilog-a language reference manual","year":"1996","journal-title":"Open Verilog International Los Gatos"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2003.1173054"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/TIM.2005.847343"},{"key":"5","first-page":"996","article-title":"an all-digital built-in self-test for high-speed phase-locked loops","volume":"54","author":"kim","year":"2005","journal-title":"IEEE Transactions on Circuits and Systems"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2004.1387339"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2001.929760"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/APASIC.2004.1349411"}],"event":{"name":"2007 IEEE International Test Conference","location":"Santa Clara, CA, USA","start":{"date-parts":[[2007,10,21]]},"end":{"date-parts":[[2007,10,26]]}},"container-title":["2007 IEEE International Test Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4437545\/4437546\/04437606.pdf?arnumber=4437606","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,6,12]],"date-time":"2026-06-12T20:53:53Z","timestamp":1781297633000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4437606\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007]]},"references-count":23,"URL":"https:\/\/doi.org\/10.1109\/test.2007.4437606","relation":{},"subject":[],"published":{"date-parts":[[2007]]}}}