{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,4]],"date-time":"2025-11-04T10:15:40Z","timestamp":1762251340362},"reference-count":29,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2007]]},"DOI":"10.1109\/test.2007.4437634","type":"proceedings-article","created":{"date-parts":[[2008,1,29]],"date-time":"2008-01-29T15:41:30Z","timestamp":1201621290000},"page":"1-10","source":"Crossref","is-referenced-by-count":2,"title":["California scan architecture for high quality and low power testing"],"prefix":"10.1109","author":[{"family":"Kyoung Youn Cho","sequence":"first","affiliation":[]},{"given":"Subhasish","family":"Mitra","sequence":"additional","affiliation":[]},{"given":"Edward J.","family":"McCluskey","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.2004.1299220"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1998.743172"},{"journal-title":"Logic Design Principles with Emphasis on Testable Semicustom Circuits","year":"1986","author":"mccluskey","key":"18"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.2003.1197675"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1995.529895"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1999.766675"},{"key":"14","first-page":"66","article-title":"evaluation of test metrics: stuck-at, bridge coverage estimate and gate exhaustive","author":"guo","year":"2006","journal-title":"Proc VLSI Test Symp"},{"key":"11","article-title":"delay-fault simulation","author":"eichelberger","year":"1991","journal-title":"Structured Logic Testing"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1999.805616"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.2000.843824"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2002.1009155"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1109\/43.238615"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1994.292299"},{"key":"24","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2001.966687"},{"key":"25","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1270887"},{"year":"0","key":"26"},{"journal-title":"VLSI Test Principles and Architectures","year":"2006","key":"27"},{"key":"28","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1973.223600"},{"key":"29","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1270873"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.842885"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/54.867895"},{"key":"10","first-page":"462","article-title":"a logic design structure for lsi testability","author":"eichelberger","year":"1977","journal-title":"Proc Design Automation Conf"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2004.1387328"},{"key":"7","article-title":"gate exhaustive testing","author":"cho","year":"2005","journal-title":"Proc Intl Test Conf"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2004.1386971"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2004.1387387"},{"key":"4","first-page":"488","article-title":"efficient scan chain design for power minimization during scan testing under routing constraint","author":"bonhomme","year":"2003","journal-title":"Proc Intl Test Conf"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/FTCSH.1995.532648"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/54.867894"}],"event":{"name":"2007 IEEE International Test Conference","start":{"date-parts":[[2007,10,21]]},"location":"Santa Clara, CA, USA","end":{"date-parts":[[2007,10,26]]}},"container-title":["2007 IEEE International Test Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4437545\/4437546\/04437634.pdf?arnumber=4437634","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,16]],"date-time":"2017-03-16T18:57:36Z","timestamp":1489690656000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4437634\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007]]},"references-count":29,"URL":"https:\/\/doi.org\/10.1109\/test.2007.4437634","relation":{},"subject":[],"published":{"date-parts":[[2007]]}}}