{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,12]],"date-time":"2026-06-12T21:04:48Z","timestamp":1781298288032,"version":"3.54.1"},"reference-count":18,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2007]]},"DOI":"10.1109\/test.2007.4437636","type":"proceedings-article","created":{"date-parts":[[2008,1,29]],"date-time":"2008-01-29T15:41:30Z","timestamp":1201621290000},"page":"1-10","source":"Crossref","is-referenced-by-count":2,"title":["Fast and effective fault simulation for path delay faults based on selected testable paths"],"prefix":"10.1109","author":[{"family":"Dong Xiang","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"family":"Yang Zhao","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"family":"Kaiwei Li","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"family":"Hideo Fujiwara","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"17","first-page":"1","article-title":"accelerated path delay fault simulation","author":"wu","year":"1992","journal-title":"Proc IEEE VLSI Test Symp"},{"key":"18","year":"0"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1993.470630"},{"key":"16","first-page":"357","article-title":"parallel pattern fault simulation of path delay faults","author":"schulz","year":"1989","journal-title":"Proc ACM\/IEEE DAC"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/43.259947"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1992.227841"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2003.1253625"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.839488(410) 24"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/43.88928"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/43.511566"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.2003.1197650"},{"key":"10","author":"lee","year":"1993","journal-title":"On the generation of test patterns for combinational circuits"},{"key":"7","doi-asserted-by":"crossref","first-page":"1095","DOI":"10.1109\/TCAD.2002.801108","article-title":"on the non-enumerative fault simulation problem","volume":"21","author":"kagaris","year":"2002","journal-title":"IEEE Trans on CAD"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/43.644037"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/43.703822"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/12.214661"},{"key":"9","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4615-5597-1","author":"krstic","year":"1998","journal-title":"Delay Fault Testing for VLSI Circuits"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/EDTC.1995.470352"}],"event":{"name":"2007 IEEE International Test Conference","location":"Santa Clara, CA, USA","start":{"date-parts":[[2007,10,21]]},"end":{"date-parts":[[2007,10,26]]}},"container-title":["2007 IEEE International Test Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4437545\/4437546\/04437636.pdf?arnumber=4437636","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,6,12]],"date-time":"2026-06-12T20:53:53Z","timestamp":1781297633000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4437636\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/test.2007.4437636","relation":{},"subject":[],"published":{"date-parts":[[2007]]}}}