{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T05:28:07Z","timestamp":1747805287459},"reference-count":21,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008,10]]},"DOI":"10.1109\/test.2008.4700594","type":"proceedings-article","created":{"date-parts":[[2008,12,10]],"date-time":"2008-12-10T12:55:58Z","timestamp":1228913758000},"page":"1-10","source":"Crossref","is-referenced-by-count":4,"title":["Distributed Embedded Logic Analysis for Post-Silicon Validation of SOCs"],"prefix":"10.1109","author":[{"family":"Ho Fai Ko","sequence":"first","affiliation":[]},{"given":"A.B.","family":"Kinsman","sequence":"additional","affiliation":[]},{"given":"N.","family":"Nicolici","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2002.1003792"},{"journal-title":"Design Compiler","year":"2003","key":"17"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2007.373606"},{"journal-title":"MPLAB REAL ICE In-Circuit Emulator","year":"2008","key":"15"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2007.157"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/MP.2005.1405795"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2007.118"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2008.4484892"},{"journal-title":"Lauterbach","year":"2007","key":"12"},{"journal-title":"ChipScope Pro","year":"2006","key":"21"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2007.4437613"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041815"},{"journal-title":"Altera Verification Tool Signal- Tap II Embedded Logic Analyzer","year":"2006","key":"2"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1146916"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2008.4484858"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2005.186"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2007.38"},{"key":"5","article-title":"the landscape of parallel computing research: a view from berkeley","author":"asanovic","year":"2006","journal-title":"Technical Report UCB\/EECS-2006-2183 EECS Department University of California"},{"journal-title":"CoreSight Onchip Debug and Trace Technology","year":"2008","key":"4"},{"journal-title":"System Navigator Pro","year":"2008","key":"9"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2005.1583986"}],"event":{"name":"2008 IEEE International Test Conference","start":{"date-parts":[[2008,10,28]]},"location":"Santa Clara, CA","end":{"date-parts":[[2008,10,30]]}},"container-title":["2008 IEEE International Test Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4690905\/4700527\/04700594.pdf?arnumber=4700594","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,17]],"date-time":"2017-03-17T12:12:20Z","timestamp":1489752740000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4700594\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,10]]},"references-count":21,"URL":"https:\/\/doi.org\/10.1109\/test.2008.4700594","relation":{},"subject":[],"published":{"date-parts":[[2008,10]]}}}