{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T07:36:21Z","timestamp":1729668981466,"version":"3.28.0"},"reference-count":29,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008,10]]},"DOI":"10.1109\/test.2008.4700610","type":"proceedings-article","created":{"date-parts":[[2008,12,10]],"date-time":"2008-12-10T17:55:58Z","timestamp":1228931758000},"page":"1-10","source":"Crossref","is-referenced-by-count":9,"title":["\"Plug & Test\" at System Level via Testable TLM Primitives"],"prefix":"10.1109","author":[{"given":"H.","family":"Alemzadeh","sequence":"first","affiliation":[]},{"given":"S.","family":"Di Carlo","sequence":"additional","affiliation":[]},{"given":"F.","family":"Refan","sequence":"additional","affiliation":[]},{"given":"P.","family":"Prinetto","sequence":"additional","affiliation":[]},{"given":"Z.","family":"Navabi","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2000.835171"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/43.55189"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/ICVD.2000.812625"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/43.712102"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/92.974896"},{"key":"13","first-page":"253","article-title":"test point insertion for scan-based bist","author":"seiss","year":"1991","journal-title":"Proc European Test Conf"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1996.510828"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1996.557079"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1989.82333"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/43.784124"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1995.528807"},{"key":"22","first-page":"162","article-title":"testability analysis and insertion for rtl circuits based on pseudorandom bist.","author":"carletta","year":"1995","journal-title":"Proc IEEE International Conference on Computer Design pages"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2000.894214"},{"key":"24","article-title":"rtl test point insertion to reduce delay test volume","author":"fang","year":"0","journal-title":"Proceedings of VLSI Test Symposium 2007"},{"key":"25","first-page":"163","volume":"25","author":"harmanani","year":"2000","journal-title":"An Approach for Redesign for Testability at the Register-Transfer Level"},{"key":"26","doi-asserted-by":"publisher","DOI":"10.1093\/ietisy\/e88-d.8.1940"},{"journal-title":"OSCI SystemC TLM 2 0 Standard","year":"0","key":"27"},{"key":"28","article-title":"system level design languages","author":"mirkhani","year":"2006","journal-title":"The VLSI Handbook"},{"journal-title":"Transaction Level Modelling in SystemC","year":"2004","author":"rose","key":"29"},{"journal-title":"Digital SystemsTesting and Testable Design","year":"1990","author":"abramovici","key":"3"},{"journal-title":"Transaction-Level Modeling With SystemC TLM Concepts and Applications for Embedded Systems","year":"2005","key":"2"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/ICVD.1998.646598"},{"key":"1","first-page":"131","author":"gro?tker","year":"2002","journal-title":"System Design with SystemC"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/12.54847"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1145\/307418.307545"},{"key":"5","doi-asserted-by":"crossref","first-page":"276","DOI":"10.1109\/TC.2004.1261835","article-title":"partial scan design based on circuit state information","volume":"53","author":"xiang","year":"2004","journal-title":"IEEE Trans Computers"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2005.88"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1991.185287"},{"key":"8","doi-asserted-by":"crossref","first-page":"81","DOI":"10.1145\/196244.196285","article-title":"an exact algorithm for selecting partial scan flip-flops","author":"chakradhar","year":"1994","journal-title":"31st Design Automation Conference"}],"event":{"name":"2008 IEEE International Test Conference","start":{"date-parts":[[2008,10,28]]},"location":"Santa Clara, CA","end":{"date-parts":[[2008,10,30]]}},"container-title":["2008 IEEE International Test Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4690905\/4700527\/04700610.pdf?arnumber=4700610","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,18]],"date-time":"2017-06-18T14:37:28Z","timestamp":1497796648000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4700610\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,10]]},"references-count":29,"URL":"https:\/\/doi.org\/10.1109\/test.2008.4700610","relation":{},"subject":[],"published":{"date-parts":[[2008,10]]}}}