{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T13:56:36Z","timestamp":1725630996511},"reference-count":18,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008,10]]},"DOI":"10.1109\/test.2008.4700642","type":"proceedings-article","created":{"date-parts":[[2008,12,10]],"date-time":"2008-12-10T12:55:58Z","timestamp":1228913758000},"page":"1-10","source":"Crossref","is-referenced-by-count":23,"title":["Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model"],"prefix":"10.1109","author":[{"given":"S.","family":"Hillebrecht","sequence":"first","affiliation":[]},{"given":"I.","family":"Polian","sequence":"additional","affiliation":[]},{"given":"P.","family":"Engelke","sequence":"additional","affiliation":[]},{"given":"B.","family":"Becker","sequence":"additional","affiliation":[]},{"given":"M.","family":"Keim","sequence":"additional","affiliation":[]},{"family":"Wu-Tung Cheng","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2008.19"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.2003.1197631"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/12.754998"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2000.894196"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-005-5287-6"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/43.856980"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1997.639668"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2007.72"},{"journal-title":"Critical Reliability Challenges for the International Technology Roadmap for Semiconductors (ITRS)","year":"2003","author":"blish","key":"3"},{"journal-title":"Copper-Fundamental Mechanisms for Microelectronis Applications","year":"2000","author":"murarka","key":"2"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2004.1386929"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041766"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.907255"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.1998.741618"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/43.177407"},{"key":"4","first-page":"143","article-title":"fault modelling of gate oxide short, floating gate and bridging failures in cmos circuits","author":"champac","year":"1991","journal-title":"Euro Test Conf"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2008.30"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.2005.64"}],"event":{"name":"2008 IEEE International Test Conference","start":{"date-parts":[[2008,10,28]]},"location":"Santa Clara, CA","end":{"date-parts":[[2008,10,30]]}},"container-title":["2008 IEEE International Test Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4690905\/4700527\/04700642.pdf?arnumber=4700642","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,17]],"date-time":"2017-03-17T14:02:21Z","timestamp":1489759341000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4700642\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,10]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/test.2008.4700642","relation":{},"subject":[],"published":{"date-parts":[[2008,10]]}}}