{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T08:51:58Z","timestamp":1725612718505},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,11]]},"DOI":"10.1109\/test.2010.5699212","type":"proceedings-article","created":{"date-parts":[[2011,1,21]],"date-time":"2011-01-21T20:20:08Z","timestamp":1295641208000},"page":"1-10","source":"Crossref","is-referenced-by-count":5,"title":["Towards effective and compression-friendly test of memory interface logic"],"prefix":"10.1109","author":[{"given":"V.R.","family":"Devanathan","sequence":"first","affiliation":[]},{"given":"Alan","family":"Hales","sequence":"additional","affiliation":[]},{"given":"Sumant","family":"Kale","sequence":"additional","affiliation":[]},{"given":"Dharmesh","family":"Sonkar","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"TetraMAX ATPG User Guide Synopsys Inc 2009","article-title":"Test Pattern Data","year":"2009","key":"ref10"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041869"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI.Design.2010.17"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2005.1494081"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2006.261012"},{"key":"ref4","first-page":"31","article-title":"On Correlating Structural Test with Functional Tests for Speed Binning of High Performance Design","author":"zeng","year":"2004","journal-title":"Proc IEEE International Test Conference"},{"key":"ref3","article-title":"Transition Test on UltraSPARC T2 Microprocessor","author":"chen","year":"2008","journal-title":"Proc IEEE International Test Conference"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1998.743142"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2003.1232255"},{"journal-title":"Testing Around Memories - an inside look","year":"0","author":"jindal","key":"ref8"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1999.805812"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687480"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775920"},{"journal-title":"Scan and ATPG Process Guide Mentor Graphics Inc 8 2009_4","article-title":"Testing RAM and ROM","year":"2009","key":"ref9"}],"event":{"name":"2010 IEEE International Test Conference (ITC)","start":{"date-parts":[[2010,11,2]]},"location":"Austin, TX, USA","end":{"date-parts":[[2010,11,4]]}},"container-title":["2010 IEEE International Test Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5684496\/5699173\/05699212.pdf?arnumber=5699212","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T09:49:26Z","timestamp":1490089766000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5699212\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,11]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/test.2010.5699212","relation":{},"subject":[],"published":{"date-parts":[[2010,11]]}}}