{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,31]],"date-time":"2025-10-31T07:20:24Z","timestamp":1761895224861},"reference-count":28,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,11]]},"DOI":"10.1109\/test.2010.5699217","type":"proceedings-article","created":{"date-parts":[[2011,1,21]],"date-time":"2011-01-21T20:20:08Z","timestamp":1295641208000},"page":"1-9","source":"Crossref","is-referenced-by-count":23,"title":["Modeling TSV open defects in 3D-stacked DRAM"],"prefix":"10.1109","author":[{"given":"Li","family":"Jiang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yuxi","family":"Liu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lian","family":"Duan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yuan","family":"Xie","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Qiang","family":"Xu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","article-title":"3D Super-Via for Memory Applications","author":"sangki","year":"2007","journal-title":"In Micro-Systems Packaging Initiative Packaging Workshop (MSPI)"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2008.4541535"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2008.4681638"},{"journal-title":"Technology Roadmap for Semiconductors (ITRS) 2009","article-title":"International","year":"2009","key":"ref13"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/43.177407"},{"key":"ref15","article-title":"High-Density Memory Utilizing Multiplexers to Reduce Bitline Pitch Constraints","author":"hilbert","year":"2002","journal-title":"US Patent"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2006.346849"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1988.207820"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1994.527999"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/66.827347"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2002.1011171"},{"key":"ref4","article-title":"Memory Systems: Cache, DRAM, Disk","author":"jacob","year":"2007","journal-title":"Morgan Kaufmann"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2001.915069"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2000.894234"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.15"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.134"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/43.811326"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1996.510888"},{"key":"ref2","article-title":"Testing Semiconductor Memories: Theory and Practice","author":"van de goor","year":"1998","journal-title":"ComTex Publishing"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/43.811326"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/78949.78950"},{"key":"ref20","article-title":"Techniques for Producing 3D ICs with High-density Interconnect","author":"gupta","year":"2004","journal-title":"Proc Int VLSI Multilevel Interconnection Conf"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2006.203"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/MTDT.2004.1327984"},{"key":"ref24","first-page":"130","article-title":"8Gb 3D DDR3 Dram Using Through-Silicon-Via Technology","author":"kang","year":"2009","journal-title":"Internat Solid-State Circuits Conference (ISSCC) Proc of"},{"journal-title":"Leo FaStack 1Gb DDR SDRAM Datasheet","article-title":"Tezzaron Semiconductors","year":"2002","key":"ref23"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041766"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.136"}],"event":{"name":"2010 IEEE International Test Conference (ITC)","start":{"date-parts":[[2010,11,2]]},"location":"Austin, TX, USA","end":{"date-parts":[[2010,11,4]]}},"container-title":["2010 IEEE International Test Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5684496\/5699173\/05699217.pdf?arnumber=5699217","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T09:52:32Z","timestamp":1490089952000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5699217\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,11]]},"references-count":28,"URL":"https:\/\/doi.org\/10.1109\/test.2010.5699217","relation":{},"subject":[],"published":{"date-parts":[[2010,11]]}}}