{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T08:49:47Z","timestamp":1725612587638},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,11]]},"DOI":"10.1109\/test.2010.5699267","type":"proceedings-article","created":{"date-parts":[[2011,1,21]],"date-time":"2011-01-21T15:20:08Z","timestamp":1295623208000},"page":"1-10","source":"Crossref","is-referenced-by-count":1,"title":["A fast and highly accurate path delay emulation framework for logic-emulation of timing speculation"],"prefix":"10.1109","author":[{"given":"Shuou","family":"Nomura","sequence":"first","affiliation":[]},{"given":"Karthikeyan","family":"Sankaralingam","sequence":"additional","affiliation":[]},{"given":"Ranganathan","family":"Sankaralingam1","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"System on Chip Test Architectures","year":"2007","author":"wang","key":"ref10"},{"journal-title":"Essentials of Electronic Testing for Digital Memory and Mixed-Signal VLSI Circuits","year":"2000","author":"bushnell","key":"ref11"},{"key":"ref12","article-title":"A Neutral Netlist of 10 Combinatorial Benchmark Circuits and a Target translator in Fortran","author":"brglez","year":"1985","journal-title":"International Symposium on Circuits and Systems Special Session on ATPG and Fault Simulation"},{"year":"0","key":"ref13"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346196"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5457059"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1816026"},{"key":"ref4","doi-asserted-by":"crossref","DOI":"10.1109\/PACT.2007.4336213","article-title":"Paceline: Improving Single- Thread Performance in Nanoscale CMPs through Core Overclocking","author":"greskamp","year":"2007","journal-title":"International Conference on Parallel Architecture and Compilation Techniques"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2010.5433922"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/43.712103"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/378993.379247"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2008.4751886"},{"key":"ref7","article-title":"Model for Delay Faults based upon Paths","author":"smith","year":"1985","journal-title":"IEEE International Test Conference"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2010.5433919"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253179"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/1228784.1228881"}],"event":{"name":"2010 IEEE International Test Conference (ITC 2010)","start":{"date-parts":[[2010,11,2]]},"location":"Austin, TX","end":{"date-parts":[[2010,11,4]]}},"container-title":["2010 IEEE International Test Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5684496\/5699173\/05699267.pdf?arnumber=5699267","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,2,5]],"date-time":"2020-02-05T16:11:32Z","timestamp":1580919092000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/5699267\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,11]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/test.2010.5699267","relation":{},"subject":[],"published":{"date-parts":[[2010,11]]}}}