{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T10:38:46Z","timestamp":1761647926654,"version":"3.28.0"},"reference-count":46,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,9]]},"DOI":"10.1109\/test.2011.6139145","type":"proceedings-article","created":{"date-parts":[[2012,1,31]],"date-time":"2012-01-31T16:37:40Z","timestamp":1328027860000},"page":"1-8","source":"Crossref","is-referenced-by-count":11,"title":["Low power compression utilizing clock-gating"],"prefix":"10.1109","author":[{"given":"Janusz","family":"Rajski","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Elham K.","family":"Moghaddam","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sudhakar M.","family":"Reddy","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref42a","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2002.1033791"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.2000.843824"},{"key":"ref38","article-title":"How power-aware test improves reliability and yield","author":"shi","year":"2004","journal-title":"EE Times EDA News Online"},{"key":"ref33","first-page":"277","article-title":"Jump scan: a DFT technique for low power testing","author":"chiu","year":"2005","journal-title":"Proc VTS"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2002.1011129"},{"key":"ref31","first-page":"488","article-title":"Efficient scan chain design for power minimization during scan testing under routing constraint","author":"bonhomme","year":"2003","journal-title":"Proc ITC"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2000.894297"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2010.5699274"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2003.1240870"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.2005.49"},{"key":"ref34","doi-asserted-by":"crossref","first-page":"313","DOI":"10.1049\/ip-cdt:20000537","article-title":"Minimization of power dissipation during test application in full scan sequential circuits using primary input freezing","volume":"147","author":"nicolici","year":"2000","journal-title":"IEE Proc Computers Digital Techniques"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2004.1386971"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2002.807895"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2001.990291"},{"key":"ref12","first-page":"928","article-title":"On the generation of scan-based test sets with reachable states for testing under functional operation conditions","author":"pomeranz","year":"2004","journal-title":"Proceedings 41st Design Automation Conference 2004 DAC"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2010.5469580"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2002.1013896"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2008.4700585"},{"key":"ref16","first-page":"539","article-title":"New test data decompressor for low power applications","author":"czysz","year":"2007","journal-title":"Proc DAC"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2010.5699275"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2007.101"},{"key":"ref19","first-page":"58","article-title":"A new ATPG method for efficient capture power reduction during scan test","author":"wen","year":"0","journal-title":"Proc VLSI Test Symp"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.829797"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2001.923416"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2001.966687"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041775"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1271098"},{"key":"ref29","first-page":"1","article-title":"Low-capture-power test generation for scan-based at-speed testing","author":"wen","year":"2005","journal-title":"Proc ITC"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2009.5355555"},{"key":"ref8","article-title":"Preferred Fill: a scalable method to reduce capture power for scan based designs","author":"remersaro","year":"0","journal-title":"Proc ITC 2006 paper 32 3"},{"key":"ref7","first-page":"1019","article-title":"Low-capture-power test generation for scan-based at-speed testing","author":"wen","year":"2005","journal-title":"Proc ITC"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041773"},{"key":"ref9","first-page":"156","author":"li","year":"2005","journal-title":"On reducing peak current and power during test"},{"key":"ref1","first-page":"237","article-title":"LFSR-coded test patterns for scan designs","author":"koenemann","year":"1991","journal-title":"Proc Eur Test Conf"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt:20070144"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2002.800460"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2008.33"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2030353"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1999.805616"},{"key":"ref24","first-page":"468","article-title":"A Low power pseudo-random BIST technique","author":"basturkmen","year":"2002","journal-title":"Proc ICCD"},{"key":"ref41","first-page":"49","article-title":"Low power serial built-in self-test","author":"hertwig","year":"1998","journal-title":"Proc ETW"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2001.923456"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/12.663775"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1271091"},{"key":"ref43","first-page":"834","article-title":"Generation of low power dissipation and high fault coverage patterns for scan-based BIST","author":"wang","year":"0"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2006.297695"}],"event":{"name":"2011 IEEE International Test Conference (ITC)","start":{"date-parts":[[2011,9,20]]},"location":"Anaheim, CA, USA","end":{"date-parts":[[2011,9,22]]}},"container-title":["2011 IEEE International Test Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6132473\/6139126\/06139145.pdf?arnumber=6139145","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,20]],"date-time":"2017-06-20T09:36:53Z","timestamp":1497951413000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6139145\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,9]]},"references-count":46,"URL":"https:\/\/doi.org\/10.1109\/test.2011.6139145","relation":{},"subject":[],"published":{"date-parts":[[2011,9]]}}}