{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,1]],"date-time":"2025-10-01T15:24:38Z","timestamp":1759332278736,"version":"3.28.0"},"reference-count":37,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,9]]},"DOI":"10.1109\/test.2011.6139156","type":"proceedings-article","created":{"date-parts":[[2012,1,31]],"date-time":"2012-01-31T21:37:40Z","timestamp":1328045860000},"page":"1-10","source":"Crossref","is-referenced-by-count":56,"title":["End-to-end error correction and online diagnosis for on-chip networks"],"prefix":"10.1109","author":[{"given":"Saeed","family":"Shamshiri","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Amirali","family":"Ghofrani","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kwang-Ting","family":"Cheng","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"ref33","DOI":"10.1109\/TNS.2005.860675"},{"doi-asserted-by":"publisher","key":"ref32","DOI":"10.1109\/IEDM.2003.1269335"},{"doi-asserted-by":"publisher","key":"ref31","DOI":"10.1109\/TDMR.2005.856487"},{"doi-asserted-by":"publisher","key":"ref30","DOI":"10.1109\/TEST.2010.5699220"},{"doi-asserted-by":"publisher","key":"ref37","DOI":"10.1109\/VTS.2010.5469579"},{"doi-asserted-by":"publisher","key":"ref36","DOI":"10.1109\/IPDPS.2005.323"},{"doi-asserted-by":"publisher","key":"ref35","DOI":"10.1155\/2007\/95348"},{"doi-asserted-by":"publisher","key":"ref34","DOI":"10.1109\/NOCS.2009.5071441"},{"year":"2009","journal-title":"International Technology Roadmap for Semiconductors(I T R S)","key":"ref10"},{"doi-asserted-by":"publisher","key":"ref11","DOI":"10.1109\/MDT.2005.104"},{"doi-asserted-by":"publisher","key":"ref12","DOI":"10.1109\/ISVLSI.2003.1183347"},{"doi-asserted-by":"publisher","key":"ref13","DOI":"10.1109\/ASPDAC.2003.1195021"},{"doi-asserted-by":"publisher","key":"ref14","DOI":"10.1109\/DSN.2006.35"},{"key":"ref15","article-title":"Self-timed NoC links using combinations of fault tolerance methods","author":"lehtonen","year":"2007","journal-title":"Proc IEEE Design Automation and Test in Europe"},{"key":"ref16","first-page":"331","article-title":"Quantitative cost modeling of error protection for network-on-chip","author":"neuenhahn","year":"2007","journal-title":"Proc ProRISK Workshop"},{"doi-asserted-by":"publisher","key":"ref17","DOI":"10.1109\/ITNG.2007.129"},{"doi-asserted-by":"publisher","key":"ref18","DOI":"10.1109\/VTS.2009.34"},{"doi-asserted-by":"publisher","key":"ref19","DOI":"10.1109\/ESSCIRC.2008.4681832"},{"doi-asserted-by":"publisher","key":"ref28","DOI":"10.1109\/18.54888"},{"doi-asserted-by":"publisher","key":"ref4","DOI":"10.1109\/MC.2005.379"},{"doi-asserted-by":"publisher","key":"ref27","DOI":"10.1109\/TIT.2004.840890"},{"doi-asserted-by":"publisher","key":"ref3","DOI":"10.1145\/1095408.1095418"},{"key":"ref6","first-page":"98","article-title":"An 80-tile 1.28TFLOPS network-on-chip in 65nm CMOS","author":"vangal","year":"2007","journal-title":"Proc IEEE Int Solid-State Circuits Conference"},{"doi-asserted-by":"publisher","key":"ref29","DOI":"10.1002\/ett.4460030505"},{"key":"ref5","first-page":"49","article-title":"The design and implementation of a first-generation CELL processor – A multi-core SoC","author":"pham","year":"2005","journal-title":"Proc IEEE Int Conf Integr Circuit Des Technol"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1109\/2.976921"},{"year":"0","journal-title":"NVIDIA Quadro FX 5600","key":"ref7"},{"key":"ref2","first-page":"248","article-title":"Clock rate versus IPC: the end of the road for conventional microarchitectures","author":"agarwal","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"year":"2006","author":"de micheli","journal-title":"NetWorks On Chips","key":"ref9"},{"key":"ref1","first-page":"40","article-title":"Top 11 technologies of the decade; #5: Multicore CPUs","volume":"48","author":"moore","year":"2011","journal-title":"IEEE Spectrum"},{"doi-asserted-by":"publisher","key":"ref20","DOI":"10.1109\/ICECS.2008.4674921"},{"doi-asserted-by":"publisher","key":"ref22","DOI":"10.1109\/TIT.1959.1057524"},{"doi-asserted-by":"publisher","key":"ref21","DOI":"10.1109\/TNS.2007.892119"},{"key":"ref24","first-page":"291","article-title":"A problem in binary encoding","author":"gilbert","year":"0","journal-title":"Proc of a Symposium in Applied Mathematics"},{"doi-asserted-by":"publisher","key":"ref23","DOI":"10.1109\/TIT.1960.1057558"},{"doi-asserted-by":"publisher","key":"ref26","DOI":"10.1109\/18.681317"},{"doi-asserted-by":"publisher","key":"ref25","DOI":"10.1137\/0108018"}],"event":{"name":"2011 IEEE International Test Conference (ITC)","start":{"date-parts":[[2011,9,20]]},"location":"Anaheim, CA, USA","end":{"date-parts":[[2011,9,22]]}},"container-title":["2011 IEEE International Test Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6132473\/6139126\/06139156.pdf?arnumber=6139156","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T19:30:22Z","timestamp":1490124622000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6139156\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,9]]},"references-count":37,"URL":"https:\/\/doi.org\/10.1109\/test.2011.6139156","relation":{},"subject":[],"published":{"date-parts":[[2011,9]]}}}