{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:51:59Z","timestamp":1759146719850},"reference-count":28,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,9]]},"DOI":"10.1109\/test.2011.6139162","type":"proceedings-article","created":{"date-parts":[[2012,1,31]],"date-time":"2012-01-31T21:37:40Z","timestamp":1328045860000},"page":"1-8","source":"Crossref","is-referenced-by-count":18,"title":["A novel scan segmentation design method for avoiding shift timing failure in scan testing"],"prefix":"10.1109","author":[{"given":"Yuta","family":"Yamato","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiaoqing","family":"Wen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael A.","family":"Kochte","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kohei","family":"Miyase","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Seiji","family":"Kajihara","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Laung-Terng","family":"Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","article-title":"On Low-Capture-Power Test Generation for Scan Testing","author":"wen","year":"2005","journal-title":"Proc IEEE VLSI Test Symp"},{"key":"ref11","article-title":"Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs","author":"remersaro","year":"2006","journal-title":"Proc IEEE Intl Test Conf"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2009.22"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/PRDC.2009.21"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1999.805616"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1999.766696"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/DELTA.2002.994606"},{"key":"ref17","first-page":"521","article-title":"Scan Test Planning for Power Reduction","author":"imhof","year":"2007","journal-title":"Proc Design Automation Conf"},{"key":"ref18","first-page":"488","article-title":"Efficient Scan Chain Design for Power Minimization during Scan Testing under Routing Constraint","author":"bonhomme","year":"2003","journal-title":"Proc IEEE IntI Test Conf"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2000.894297"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2011.5783778"},{"key":"ref4","article-title":"Diagnosis of Scan Chain Failures","author":"wu","year":"1998","journal-title":"Proc IEEE Int Symp Defect and Fault Tolerance"},{"year":"0","key":"ref27"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1270854"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2001.966687"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2002.1003802"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1166\/jolpe.2008.274"},{"journal-title":"Power-Aware Testing and Test Strategies for Low Power Devices","year":"2009","author":"girard","key":"ref7"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041869"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1271098"},{"journal-title":"VLSI Test Principles and Architectures Design for Testability","year":"2006","author":"wang","key":"ref1"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2001.990291"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.829797"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2001.923454"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2005.74"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1270873"},{"key":"ref26","first-page":"323","article-title":"Power and Noise Aware Test Using Preliminary Estimation","author":"noda","year":"2005","journal-title":"Proc VLSI Design Automation and Test"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/5.929649"}],"event":{"name":"2011 IEEE International Test Conference (ITC)","start":{"date-parts":[[2011,9,20]]},"location":"Anaheim, CA, USA","end":{"date-parts":[[2011,9,22]]}},"container-title":["2011 IEEE International Test Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6132473\/6139126\/06139162.pdf?arnumber=6139162","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T19:34:33Z","timestamp":1490124873000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6139162\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,9]]},"references-count":28,"URL":"https:\/\/doi.org\/10.1109\/test.2011.6139162","relation":{},"subject":[],"published":{"date-parts":[[2011,9]]}}}