{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T05:28:33Z","timestamp":1747805313757,"version":"3.28.0"},"reference-count":36,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,9]]},"DOI":"10.1109\/test.2011.6139164","type":"proceedings-article","created":{"date-parts":[[2012,1,31]],"date-time":"2012-01-31T16:37:40Z","timestamp":1328027860000},"page":"1-10","source":"Crossref","is-referenced-by-count":9,"title":["State of the art low capture power methodology"],"prefix":"10.1109","author":[{"given":"Swapnil","family":"Bahl","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"R.","family":"Mattiuzzo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shray","family":"Khullar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Akhil","family":"Garg","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S.","family":"Graniello","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Khader S.","family":"Abdel-Hafez","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Salvatore","family":"Talluto","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"crossref","first-page":"363","DOI":"10.1109\/TCAD.2002.807890","article-title":"Test pattern generation and clock disabling for simultaneous test time and power reduction","volume":"22","author":"chen","year":"2003","journal-title":"Computer-Aided Design of Integrated Circuits and Systems IEEE Transactions on"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2009.5355649"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2008.27"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2008.4700585"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2005.863742"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2010.124"},{"key":"ref34","first-page":"2","article-title":"Low cost Design-for-Testability features for System-on-Chip: Case study","volume":"2","author":"cai","year":"2010","journal-title":"Computer Engineering and Technology (ICCET) 2010 2nd International Conference on"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/224081.224083"},{"key":"ref11","first-page":"944","article-title":"FSM decomposition for power gating design automation in sequential circuits","volume":"2","author":"liu","year":"2005","journal-title":"ASIC 2005 ASICON 2005 6th International Conference On"},{"key":"ref12","first-page":"253","article-title":"A gated clock scheme for low power scan testing of logic ICs or embedded cores","author":"bonhomme","year":"2001","journal-title":"Proc 10th Asian Test Symp 2001"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1993.313316"},{"key":"ref14","first-page":"265","article-title":"On low-capture-power test generation for scan testing","author":"wen","year":"2005","journal-title":"VLSI Test Symposium 2005 Proceedings 23rd IEEE"},{"key":"ref15","first-page":"355","article-title":"Minimizing power consumption in scan testing: pattern generation and DFT techniques","author":"butler","year":"2004","journal-title":"Test Conference 2004 Proceedings ITC 2004 International"},{"key":"ref16","first-page":"271","article-title":"scheduling of tests","author":"chou","year":"1994","journal-title":"Proceedings of the Seventh International Conference"},{"key":"ref17","first-page":"453","article-title":"A test pattern generation methodology for low power consumption","author":"como","year":"1998","journal-title":"VLSI Test Symposium 1998 Proceedings 16th IEEE"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/43.736572"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1998.706917"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2001.923454"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1270873"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2001.923456"},{"key":"ref3","first-page":"848","article-title":"DS-LFSR: a new BIST TPG for low heat dissipation","year":"1997","journal-title":"Test Conference 1997 Proceedings International"},{"key":"ref6","doi-asserted-by":"crossref","first-page":"35","DOI":"10.1109\/ISQED.2003.1194706","article-title":"Analysis of IR-drop scaling with implications for deep submicron P\/G network designs","author":"ajami","year":"2003","journal-title":"Quality Electronic Design 2003 Proceedings Fourth International Symposium on"},{"key":"ref29","first-page":"45","article-title":"ATPG power reduction using clock gate default constraints","author":"illman","year":"2008","journal-title":"Proc 1st International Workshop on the Implications of Low Power Design on Test and Reliability"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1997.597219"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1271098"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2006.297642"},{"article-title":"Essentials of Electronic Testing","year":"2000","author":"bushnell","key":"ref2"},{"key":"ref9","doi-asserted-by":"crossref","first-page":"622","DOI":"10.1109\/DAC.2003.1219093","article-title":"Clock-tree power optimization based on RTL clock-gating","author":"donno","year":"2003","journal-title":"Design Automation Conference 2003 Proceedings"},{"article-title":"Design-for-Test for Digital IC's and Embedded Core Systems","year":"1999","author":"crouch","key":"ref1"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/GLSV.1999.757369"},{"key":"ref22","first-page":"156","article-title":"On reducing peak current and power during test","year":"2005","journal-title":"VLS! 2005 Proceedings IEEE Computer Society Annual Symposium on"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:20045139"},{"key":"ref24","first-page":"6","article-title":"A new ATPG method for efficient capture power reduction during scan testing","author":"wen","year":"2006","journal-title":"VLSI Test Symposium 2006 Proceedings 24th IEEE"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/VLSISOC.2006.313222"},{"key":"ref26","first-page":"793","article-title":"Low Shift and Capture Power Scan Tests","author":"santiago remersaro","year":"2007","journal-title":"VLSI Design 2007 Held Jointly with 6th International Conference on Embedded Systems 20th International Conference on"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2006.297694"}],"event":{"name":"2011 IEEE International Test Conference (ITC)","start":{"date-parts":[[2011,9,20]]},"location":"Anaheim, CA, USA","end":{"date-parts":[[2011,9,22]]}},"container-title":["2011 IEEE International Test Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6132473\/6139126\/06139164.pdf?arnumber=6139164","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,20]],"date-time":"2017-06-20T09:36:53Z","timestamp":1497951413000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6139164\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,9]]},"references-count":36,"URL":"https:\/\/doi.org\/10.1109\/test.2011.6139164","relation":{},"subject":[],"published":{"date-parts":[[2011,9]]}}}