{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T20:35:24Z","timestamp":1725568524245},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,9]]},"DOI":"10.1109\/test.2011.6139167","type":"proceedings-article","created":{"date-parts":[[2012,1,31]],"date-time":"2012-01-31T16:37:40Z","timestamp":1328027860000},"page":"1-10","source":"Crossref","is-referenced-by-count":0,"title":["Transition test bring-up and diagnosis on UltraSPARC&lt;sup&gt;TM&lt;\/sup&gt; processors"],"prefix":"10.1109","author":[{"given":"Liang-Chi","family":"Chen","sequence":"first","affiliation":[]},{"given":"Peter","family":"Dahlgren","sequence":"additional","affiliation":[]},{"given":"Paul","family":"Dickinson","sequence":"additional","affiliation":[]},{"given":"Scott","family":"Davidson","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","first-page":"108","article-title":"An 8-Core 64-Thread 64b Power-Efficient SPARC SoC","author":"nawathe","year":"2007","journal-title":"Proc Int'l Solid-State Circuits Conf"},{"doi-asserted-by":"publisher","key":"ref3","DOI":"10.1109\/VTS.2005.87"},{"key":"ref10","first-page":"31","article-title":"On correlating structural tests with functional tests for speed binning of high performance design","author":"zeng","year":"2004","journal-title":"Proc Int'l Test Conf"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.1109\/JSSC.2010.2080491"},{"year":"0","author":"chen","article-title":"Transition test on UltraSPARC T2 microprocessor","key":"ref11"},{"year":"0","author":"molyneaux","article-title":"Design for testability features of the SUN micro systems Niagara2 CMP\/CMT SPARC chip","key":"ref5"},{"year":"0","author":"chen","article-title":"Using transition test on understanding timing behavior of logic circuits on UltraSPARC T2 family","key":"ref12"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1109\/VTS.2002.1011103"},{"doi-asserted-by":"publisher","key":"ref7","DOI":"10.1109\/VTEST.2000.843819"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1109\/TEST.1999.805623"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1109\/MDT.2003.1232255"},{"key":"ref1","first-page":"406","article-title":"Testability features of AMD-K6 microprocessor","author":"fetherston","year":"1997","journal-title":"Proc Int'l Test Conf"}],"event":{"name":"2011 IEEE International Test Conference (ITC)","start":{"date-parts":[[2011,9,20]]},"location":"Anaheim, CA, USA","end":{"date-parts":[[2011,9,22]]}},"container-title":["2011 IEEE International Test Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6132473\/6139126\/06139167.pdf?arnumber=6139167","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T15:17:43Z","timestamp":1490109463000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6139167\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,9]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/test.2011.6139167","relation":{},"subject":[],"published":{"date-parts":[[2011,9]]}}}