{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T11:15:20Z","timestamp":1725534920728},"reference-count":17,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,9]]},"DOI":"10.1109\/test.2011.6139168","type":"proceedings-article","created":{"date-parts":[[2012,1,31]],"date-time":"2012-01-31T21:37:40Z","timestamp":1328045860000},"page":"1-8","source":"Crossref","is-referenced-by-count":2,"title":["Test access and the testability features of the Poulson multi-core Intel Itanium® processor"],"prefix":"10.1109","author":[{"given":"Dilip K.","family":"Bhavsar","sequence":"first","affiliation":[]},{"given":"Steve J.","family":"Poehlman","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2001.966662"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2002.1011105"},{"key":"ref12","article-title":"The good, the bad, and the ugly of silicon debug","author":"josephson","year":"2006","journal-title":"Design Automation 43rd ACM\/IEEE Conf"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2001.966676"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2009.5355542"},{"key":"ref15","article-title":"Hardware Hooks for transition scan sharacterization","author":"pant","year":"2011","journal-title":"Int Test Conf"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.859894"},{"journal-title":"IEEE 1149 1","article-title":"IEEE Standard Test Access Port and Boundary-Scan Architecture","year":"1980","key":"ref17"},{"key":"ref4","article-title":"Testing of the UltraSPARC Tl microprocessor and Its challenges","author":"tan","year":"2006","journal-title":"Int'l Test Conf"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2005.1583967"},{"key":"ref6","article-title":"Testing of Vega 2, a chip multi-processor with spare processors","author":"makar","year":"2007","journal-title":"Int'l Test Conf"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2007.4437561"},{"key":"ref8","article-title":"Tukwila - A case study in multi core DFX architecture","author":"bhavsar","year":"2005","journal-title":"Internal document"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2008.4700553"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041825"},{"key":"ref1","article-title":"A 32 nm, 3.1 Billion Transistor, 12 wide issue Itanium® Processor for Mission-Critical Servers","author":"riedlinger","year":"2011","journal-title":"International Solid-State Circuits Conference"},{"key":"ref9","article-title":"Pentium PRO microprocessor Design for Test and Debug","author":"carbine","year":"1997","journal-title":"Int'l Test Conf"}],"event":{"name":"2011 IEEE International Test Conference (ITC)","start":{"date-parts":[[2011,9,20]]},"location":"Anaheim, CA, USA","end":{"date-parts":[[2011,9,22]]}},"container-title":["2011 IEEE International Test Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6132473\/6139126\/06139168.pdf?arnumber=6139168","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T19:17:45Z","timestamp":1490123865000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6139168\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,9]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/test.2011.6139168","relation":{},"subject":[],"published":{"date-parts":[[2011,9]]}}}