{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,11]],"date-time":"2025-11-11T13:01:22Z","timestamp":1762866082731,"version":"3.41.0"},"reference-count":25,"publisher":"IEEE","license":[{"start":{"date-parts":[[2012,11,1]],"date-time":"2012-11-01T00:00:00Z","timestamp":1351728000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2012,11,1]],"date-time":"2012-11-01T00:00:00Z","timestamp":1351728000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,11]]},"DOI":"10.1109\/test.2012.6401566","type":"proceedings-article","created":{"date-parts":[[2013,1,10]],"date-time":"2013-01-10T00:26:46Z","timestamp":1357777606000},"page":"1-10","source":"Crossref","is-referenced-by-count":3,"title":["A unified method for parametric fault characterization of post-bond TSVs"],"prefix":"10.1109","author":[{"given":"Yu-Hsiang","family":"Lin","sequence":"first","affiliation":[{"name":"Electrical Engineering Department, National Tsing Hua University, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shi-Yu","family":"Huang","sequence":"additional","affiliation":[{"name":"Electrical Engineering Department, National Tsing Hua University, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kun-Han","family":"Tsai","sequence":"additional","affiliation":[{"name":"Silicon Test Solutions, Mentor Graphics"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wu-Tung","family":"Cheng","sequence":"additional","affiliation":[{"name":"Silicon Test Solutions, Mentor Graphics"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Stephen","family":"Sunter","sequence":"additional","affiliation":[{"name":"Silicon Test Solutions, Mentor Graphics"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ICMTS.2003.1197464"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2009.42"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2010.5469559"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCPMT.2011.2166961"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2008.4672039"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/96.475271"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5457218"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2011.5783749"},{"first-page":"130","article-title":"8Gb 3D DDR3 DRAM using Through-Silicon-Via Technology","volume-title":"IEEE Digest of Technical Papers of Int\u2019l Solid-State Circuits Conf.","key":"ref9"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2009.125"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/test.2007.4437621"},{"key":"ref12","first-page":"1031","article-title":"Small Delay Testing for TSVs in 3D ICs","volume-title":"IEEE Proc. of Design Automation Conf.","author":"Lin"},{"issue":"23","key":"ref13","first-page":"25","article-title":"3D Integration: Why, What, Who, When?","author":"Lu","year":"2007","journal-title":"Future Fab. International"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2008.4681638"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2005.1466154"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-007-0759-5"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2009.5355573"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1989.77002"},{"issue":"23","key":"ref19","article-title":"Impact of Wafer-Level 3D Stacking on the Yield of ICs","author":"Patti","year":"2007","journal-title":"Future Fab International"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/3DIC.2009.5306569"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2008.4700548"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1023\/A:1008365428314"},{"key":"ref23","first-page":"10240","article-title":"TSV Open Defects in 3D Integrated Circuits: Characterization, Test, and Optimal Spare Allocation","volume-title":"Proc. of Design Automation Conf.","author":"Ye"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2010.73"},{"volume-title":"CIC Referenced Flow for Cell-based IC Design","year":"2008","key":"ref25"}],"event":{"name":"2012 IEEE International Test Conference (ITC)","start":{"date-parts":[[2012,11,5]]},"location":"Anaheim, CA, USA","end":{"date-parts":[[2012,11,8]]}},"container-title":["2012 IEEE International Test Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6387511\/6401510\/06401566.pdf?arnumber=6401566","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T05:23:07Z","timestamp":1747804987000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6401566\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,11]]},"references-count":25,"URL":"https:\/\/doi.org\/10.1109\/test.2012.6401566","relation":{},"subject":[],"published":{"date-parts":[[2012,11]]}}}