{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T13:35:37Z","timestamp":1725629737995},"reference-count":19,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,11]]},"DOI":"10.1109\/test.2012.6401571","type":"proceedings-article","created":{"date-parts":[[2013,1,10]],"date-time":"2013-01-10T00:26:46Z","timestamp":1357777606000},"page":"1-10","source":"Crossref","is-referenced-by-count":15,"title":["FPGA-based synthetic instrumentation for board test"],"prefix":"10.1109","author":[{"given":"Igor","family":"Aleksejev","sequence":"first","affiliation":[]},{"given":"Artur","family":"Jutman","sequence":"additional","affiliation":[]},{"given":"Sergei","family":"Devadze","sequence":"additional","affiliation":[]},{"given":"Sergei","family":"Odintsov","sequence":"additional","affiliation":[]},{"given":"Thomas","family":"Wenzel","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"year":"0","key":"19"},{"journal-title":"ASSET InterTech","article-title":"How to test high-speed memory with non-intrusive embedded instruments\", whitepaper","year":"2012","key":"17"},{"year":"2012","key":"18"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2000.894231"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2005.86"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/IEMT.2010.5746723"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/NORCHP.2008.4738291"},{"journal-title":"IEEE Standard for Reduced-in and Enhanced-functionality Test Access Port and Boundary Scan Architecture","year":"2009","key":"11"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2007.4437656"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2008.4700559"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2008.67"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2009.5355673"},{"year":"0","key":"10"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-19137-4_8"},{"key":"6","first-page":"1","article-title":"Fast extended test access via jtag and fpgas","author":"aleksejev","year":"2009","journal-title":"Proc Int Test Conf"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/ETSYM.2004.1347572"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1999.805765"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-0367-5"},{"journal-title":"IEEE Std 1149 1-2001","article-title":"Ieee standard test access port and boundary-scan architecture","year":"2001","key":"8"}],"event":{"name":"2012 IEEE International Test Conference (ITC)","start":{"date-parts":[[2012,11,5]]},"location":"Anaheim, CA, USA","end":{"date-parts":[[2012,11,8]]}},"container-title":["2012 IEEE International Test Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6387511\/6401510\/06401571.pdf?arnumber=6401571","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,22]],"date-time":"2017-03-22T18:09:52Z","timestamp":1490206192000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6401571\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,11]]},"references-count":19,"URL":"https:\/\/doi.org\/10.1109\/test.2012.6401571","relation":{},"subject":[],"published":{"date-parts":[[2012,11]]}}}