{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T07:10:05Z","timestamp":1747811405751,"version":"3.41.0"},"reference-count":24,"publisher":"IEEE","license":[{"start":{"date-parts":[[2012,11,1]],"date-time":"2012-11-01T00:00:00Z","timestamp":1351728000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2012,11,1]],"date-time":"2012-11-01T00:00:00Z","timestamp":1351728000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,11]]},"DOI":"10.1109\/test.2012.6401577","type":"proceedings-article","created":{"date-parts":[[2013,1,10]],"date-time":"2013-01-10T00:26:46Z","timestamp":1357777606000},"page":"1-10","source":"Crossref","is-referenced-by-count":1,"title":["Testing strategies for a 9T sub-threshold SRAM"],"prefix":"10.1109","author":[{"given":"Hao-Yu","family":"Yang","sequence":"first","affiliation":[{"name":"Department of Electronics Engineering & Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan"}]},{"given":"Chen-Wei","family":"Lin","sequence":"additional","affiliation":[{"name":"Department of Electronics Engineering & Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan"}]},{"given":"Hung-Hsin","family":"Chen","sequence":"additional","affiliation":[{"name":"Department of Electronics Engineering & Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan"}]},{"given":"Mango C.-T.","family":"Chao","sequence":"additional","affiliation":[{"name":"Department of Electronics Engineering & Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan"}]},{"given":"Ming-Hsien","family":"Tu","sequence":"additional","affiliation":[{"name":"Department of Electronics Engineering & Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan"}]},{"given":"Shyh-Jye","family":"Jou","sequence":"additional","affiliation":[{"name":"Department of Electronics Engineering & Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan"}]},{"given":"Ching-Te","family":"Chuang","sequence":"additional","affiliation":[{"name":"Department of Electronics Engineering & Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan"}]}],"member":"263","reference":[{"key":"ref1","first-page":"868","article-title":"Theoretical and practical limits of dynamic voltage scaling","volume-title":"Design Automation Conference","author":"Zhai"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/1013235.1013265"},{"volume-title":"Sub-threshold Design for Ultra Low-Power Systems","year":"2006","author":"Wang","key":"ref3"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2005.1494078"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2004.1346592"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2004.1346590"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2006.1696325"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.914328"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.908005"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2011972"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/APCCAS.2008.4746384"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/APCCAS.2010.5774949"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/EIT.2011.5978615"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2011.5993652"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2007.4405723"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC.2008.4641520"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2001903"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2011.2158345"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/tc.2011.252"},{"article-title":"A 72Kb Single-Ended Disturb-Free Subthreshold SRAM with Cross-Point Data-Aware Write Word-Line, Negative Bit-Lane, and Adaptive Read Operation Timing Tracing","volume-title":"Subthreshold Microelectronics Conference","author":"Tu","key":"ref20"},{"volume-title":"Testing Semiconductor Memories, Theory and Practice","year":"1998","author":"van de Goor","key":"ref21"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ETSYM.2004.1347645"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2005.859565"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2005.1584045"}],"event":{"name":"2012 IEEE International Test Conference (ITC)","start":{"date-parts":[[2012,11,5]]},"location":"Anaheim, CA, USA","end":{"date-parts":[[2012,11,8]]}},"container-title":["2012 IEEE International Test Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6387511\/6401510\/06401577.pdf?arnumber=6401577","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T06:30:34Z","timestamp":1747809034000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6401577\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,11]]},"references-count":24,"URL":"https:\/\/doi.org\/10.1109\/test.2012.6401577","relation":{},"subject":[],"published":{"date-parts":[[2012,11]]}}}