{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T04:42:51Z","timestamp":1725770571618},"reference-count":17,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,11]]},"DOI":"10.1109\/test.2012.6401578","type":"proceedings-article","created":{"date-parts":[[2013,1,10]],"date-time":"2013-01-10T00:26:46Z","timestamp":1357777606000},"page":"1-10","source":"Crossref","is-referenced-by-count":6,"title":["Low-power SRAMs power mode control logic: Failure analysis and test solutions"],"prefix":"10.1109","author":[{"given":"L. B.","family":"Zordan","sequence":"first","affiliation":[]},{"given":"A.","family":"Bosio","sequence":"additional","affiliation":[]},{"given":"L.","family":"Dilillo","sequence":"additional","affiliation":[]},{"given":"P.","family":"Girard","sequence":"additional","affiliation":[]},{"given":"A.","family":"Todri","sequence":"additional","affiliation":[]},{"given":"A.","family":"Virazel","sequence":"additional","affiliation":[]},{"given":"N.","family":"Badereddine","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.2000.843856"},{"key":"15","article-title":"Statistical modeling for the minimum standby supply voltage of a full sram array","author":"giraud","year":"2007","journal-title":"the 23rd European Solid-State Circuits Conference"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2008.4479705"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2002.1003572"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2004.1283650"},{"key":"11","article-title":"Defect analysis in power mode control logic of low-ower srams accepted as a single page poster at","author":"zordan","year":"2012","journal-title":"IEEE ETS"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2006.47"},{"key":"3","article-title":"Embedded sram circuit design technology for a 45nm and beyond","author":"yamauchi","year":"2007","journal-title":"Proc of ASIC"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:20045084"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2002.808156"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2011.97"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2005.1584047"},{"key":"6","article-title":"Advanced test methods for srams effective solutions for dynamic fault detection in nanoscale technologie","author":"bosio","year":"2009","journal-title":"ISBN"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.2002.146699"},{"journal-title":"International Technology Roadmap for Semiconductors (ITRS)","year":"2011","key":"4"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/MTDT.2002.1029769"},{"journal-title":"Testing Semiconductor Memories Theory and Practice","year":"1991","author":"van de goor","key":"8"}],"event":{"name":"2012 IEEE International Test Conference (ITC)","start":{"date-parts":[[2012,11,5]]},"location":"Anaheim, CA, USA","end":{"date-parts":[[2012,11,8]]}},"container-title":["2012 IEEE International Test Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6387511\/6401510\/06401578.pdf?arnumber=6401578","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,22]],"date-time":"2017-03-22T18:13:40Z","timestamp":1490206420000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6401578\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,11]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/test.2012.6401578","relation":{},"subject":[],"published":{"date-parts":[[2012,11]]}}}