{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,10]],"date-time":"2025-06-10T20:05:34Z","timestamp":1749585934625,"version":"3.28.0"},"reference-count":33,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,10]]},"DOI":"10.1109\/test.2014.7035331","type":"proceedings-article","created":{"date-parts":[[2015,2,11]],"date-time":"2015-02-11T22:21:10Z","timestamp":1423693270000},"page":"1-7","source":"Crossref","is-referenced-by-count":5,"title":["Redundancy architectures for channel-based 3D DRAM yield improvement"],"prefix":"10.1109","author":[{"given":"Bing-Yang","family":"Lin","sequence":"first","affiliation":[]},{"given":"Wan-Ting","family":"Chiang","sequence":"additional","affiliation":[]},{"given":"Cheng-Wen","family":"Wu","sequence":"additional","affiliation":[]},{"given":"Mincent","family":"Lee","sequence":"additional","affiliation":[]},{"given":"Hung-Chih","family":"Lin","sequence":"additional","affiliation":[]},{"given":"Ching-Nen","family":"Peng","sequence":"additional","affiliation":[]},{"given":"Min-Jer","family":"Wang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2007.144"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/43.44511"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2013.11"},{"key":"ref30","doi-asserted-by":"crossref","first-page":"742","DOI":"10.1109\/TVLSI.2005.848824","article-title":"A built-in self-repair design for RAMs with 2-D redundancy","volume":"13","author":"li","year":"2005","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2010.5654154"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2001.990308"},{"journal-title":"Design for Testability VLSI Test Principles and Architectures","year":"2006","author":"wang","key":"ref12"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2001.966724"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2000.894250"},{"key":"ref15","first-page":"895","article-title":"At-speed built-in self-repair analyzer for embedded word-oriented memories","author":"du","year":"2004","journal-title":"Proc 17th Int Conf VLSI Des"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TR.2003.821925"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2008996"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2106812"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2008.4550031"},{"key":"ref28","first-page":"1","article-title":"Efficient test and repair architectures for 3D TSV-based random access memories","author":"lu","year":"2013","journal-title":"International Symposium on VLSI Design Automation and Test (VLSI-DAT)"},{"key":"ref4","first-page":"496","article-title":"A 1.2 V 12.8 GB\/s 2 Gb mobile wide-I\/O DRAM with 4×128 I\/Os using TSV-based stacking","author":"kim","year":"2011","journal-title":"IEEE ISSCC Dig"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2010.5654160"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2109630"},{"year":"2011","key":"ref6"},{"key":"ref29","first-page":"1","article-title":"3D-IC BISR for stacked memories using cross-die spares","author":"chi","year":"2012","journal-title":"Proc Int Symp VLSI Design Autom Test"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2008.2007472"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2012.6242474"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2164731"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2034408"},{"article-title":"MemCon Panel: Promises and Pitfalls of 3D-IC Memory Standards","year":"2013","author":"goering","key":"ref9"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024774"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2008.4550025"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2009.5355573"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/EPTC.2010.5702751"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2011.55"},{"key":"ref23","doi-asserted-by":"crossref","first-page":"104","DOI":"10.1109\/VDAT.2010.5496702","article-title":"Yield-enhancement techniques for 3D random access memories","author":"chou","year":"2010","journal-title":"International Symposium on VLSI Design Automation and Test (VLSI-DAT)"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2013.2246235"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2051466"}],"event":{"name":"2014 IEEE International Test Conference (ITC)","start":{"date-parts":[[2014,10,20]]},"location":"Seattle, WA, USA","end":{"date-parts":[[2014,10,23]]}},"container-title":["2014 International Test Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7024668\/7035243\/07035331.pdf?arnumber=7035331","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,23]],"date-time":"2017-06-23T05:21:59Z","timestamp":1498195319000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7035331\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,10]]},"references-count":33,"URL":"https:\/\/doi.org\/10.1109\/test.2014.7035331","relation":{},"subject":[],"published":{"date-parts":[[2014,10]]}}}