{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,11]],"date-time":"2025-07-11T10:36:29Z","timestamp":1752230189855,"version":"3.28.0"},"reference-count":38,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,10]]},"DOI":"10.1109\/test.2014.7035360","type":"proceedings-article","created":{"date-parts":[[2015,2,11]],"date-time":"2015-02-11T17:21:10Z","timestamp":1423675270000},"page":"1-8","source":"Crossref","is-referenced-by-count":35,"title":["FAST-BIST: Faster-than-at-Speed BIST targeting hidden delay defects"],"prefix":"10.1109","author":[{"given":"Sybille","family":"Hellebrand","sequence":"first","affiliation":[]},{"given":"Thomas","family":"Indlekofer","sequence":"additional","affiliation":[]},{"given":"Matthias","family":"Kampmann","sequence":"additional","affiliation":[]},{"given":"Michael A.","family":"Kochte","sequence":"additional","affiliation":[]},{"given":"Chang","family":"Liu","sequence":"additional","affiliation":[]},{"given":"Hans-Joachim","family":"Wunderlich","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2043570"},{"key":"ref33","first-page":"105","article-title":"Experiments at Detecting Delay Faults using Multiple Higher Frequency Clocks and Results from Neighboring Die","author":"yan","year":"2003","journal-title":"Proc IEEE Int Test Conf (ITC"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2007.4437576"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4419-8297-1"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2008.4700564"},{"key":"ref37","first-page":"31","article-title":"On correlating structural tests with functional tests for speed binning of high performance design","author":"zeng","year":"2004","journal-title":"Proc IEEE Int Test Conf (ITC"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2007.4437575"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2011.6139131"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2043591"},{"journal-title":"Benchmark information and circuits","year":"0","key":"ref10"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4684-2001-2_9"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2010.5560326"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2004.1386955"},{"key":"ref14","first-page":"1","article-title":"Failing Frequency Signature Analysis","author":"lee","year":"2008","journal-title":"Proc IEEE Int Test Conf (ITC'08)"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2006.261012"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2011.2135354"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2000.894202"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041774"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2004.1386979"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2010.5469617"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2003.1232255"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2005.1584076"},{"key":"ref3","first-page":"200","article-title":"Self-Testing of Multichip Logic Modules","author":"bardell","year":"1982","journal-title":"Proc IEEE Int Test Conf (ITC'82)"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763207"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2005.863742"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2035550"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2008.42"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2099243"},{"key":"ref2","article-title":"Defining faster-than-at-speed delay tests","volume":"2","author":"amodeo","year":"2005","journal-title":"Cadence Nanometer Test Quarterly eNewsletter"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2007.4437611"},{"key":"ref1","first-page":"198","article-title":"A Novel Framework for Faster-than-at-Speed Delay Test Considering IR-drop Effects","author":"ahmed","year":"2006","journal-title":"Proc IEEE\/ACM Int Conf on Computer Aided Design (ICCAD'06)"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1007\/s00454-010-9285-9"},{"key":"ref22","first-page":"1353","article-title":"An On-Chip Clock Generation Scheme for Faster-than-at-Speed Delay Testing","author":"pei","year":"2010","journal-title":"Proc Design and Test in Europe (DATE)"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1271094"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1270904"},{"key":"ref23","article-title":"Easily Implement PLL Clock Switching for At-Speed Test","author":"press","year":"2006","journal-title":"Chip Design Magazine"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2013.6651925"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.826558"}],"event":{"name":"2014 IEEE International Test Conference (ITC)","start":{"date-parts":[[2014,10,20]]},"location":"Seattle, WA, USA","end":{"date-parts":[[2014,10,23]]}},"container-title":["2014 International Test Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7024668\/7035243\/07035360.pdf?arnumber=7035360","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,23]],"date-time":"2017-03-23T20:36:56Z","timestamp":1490301416000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7035360\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,10]]},"references-count":38,"URL":"https:\/\/doi.org\/10.1109\/test.2014.7035360","relation":{},"subject":[],"published":{"date-parts":[[2014,10]]}}}