{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T15:14:14Z","timestamp":1730301254481,"version":"3.28.0"},"reference-count":29,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,10]]},"DOI":"10.1109\/test.2015.7342405","type":"proceedings-article","created":{"date-parts":[[2015,12,3]],"date-time":"2015-12-03T21:11:39Z","timestamp":1449177099000},"page":"1-10","source":"Crossref","is-referenced-by-count":1,"title":["On diagnosable and tunable 3D clock network design for lifetime reliability enhancement"],"prefix":"10.1109","author":[{"given":"Li","family":"Jiang","sequence":"first","affiliation":[]},{"given":"Pu","family":"Pang","sequence":"additional","affiliation":[]},{"given":"Naifeng","family":"Jing","sequence":"additional","affiliation":[]},{"given":"Sung Kyu","family":"Lim","sequence":"additional","affiliation":[]},{"given":"Xiaoyao","family":"Liang","sequence":"additional","affiliation":[]},{"given":"Qiang","family":"Xu","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2010.5654245"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488824"},{"key":"ref12","first-page":"735","article-title":"An efficient method to identify critical gates under circuit aging","author":"wang","year":"2007","journal-title":"IEEE\/ ACM International Conference on Computer-Aided Design"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2074070"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2333660.2333668"},{"key":"ref15","first-page":"434","article-title":"In-system and on-the-fly clock tuning mechanism to combat lifetime performance degradation","author":"lak","year":"2010","journal-title":"International Conference on Computer-Aided Design"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2011.5722264"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2270285"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2010.07.024"},{"key":"ref19","first-page":"292","article-title":"Clock distribution on a dual-core, multithreaded itanium®-family processor","author":"mahoney","year":"2005","journal-title":"International Solid-State Circuits Conference"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TDSC.2010.41"},{"key":"ref4","article-title":"Through-silicon via fault-tolerant clock networks for 3-d ics","volume":"32","author":"lung","year":"2013","journal-title":"Transactions on Computer-aided Ddesign of Integrated Circuits and Systems"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.812371"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCPMT.2010.2099590"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2010.2068572"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228545"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2098130"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2010.07.024"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2010.5490883"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/1148015.1148016"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2011.5784499"},{"journal-title":"International Technology Roadmap for Semiconductors 2011 Edition","article-title":"Semiconductor Industry Association (SIA)","year":"2011","key":"ref1"},{"key":"ref20","first-page":"575","article-title":"Statistical timing analysis driven post-silicon-tunable clock-tree synthesis","author":"tsai","year":"2005","journal-title":"International Conference on Computer-Aided Design"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2010.5654274"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2008.4700565"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCPMT.2013.2238581"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.5573\/JSTS.2012.12.2.139"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2209883"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2007.22"}],"event":{"name":"2015 IEEE International Test Conference (ITC)","start":{"date-parts":[[2015,10,6]]},"location":"Anaheim, CA, USA","end":{"date-parts":[[2015,10,8]]}},"container-title":["2015 IEEE International Test Conference (ITC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7331771\/7342364\/07342405.pdf?arnumber=7342405","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,24]],"date-time":"2017-03-24T21:35:40Z","timestamp":1490391340000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7342405\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,10]]},"references-count":29,"URL":"https:\/\/doi.org\/10.1109\/test.2015.7342405","relation":{},"subject":[],"published":{"date-parts":[[2015,10]]}}}