{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,3]],"date-time":"2024-09-03T23:20:59Z","timestamp":1725405659678},"reference-count":48,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,10]]},"DOI":"10.1109\/test.2015.7342422","type":"proceedings-article","created":{"date-parts":[[2015,12,3]],"date-time":"2015-12-03T21:11:39Z","timestamp":1449177099000},"page":"1-10","source":"Crossref","is-referenced-by-count":3,"title":["Cross-layer approaches for an aging-aware design of nanoscale microprocessors: Dissertation summary: IEEE TTTC E.J. McCluskey doctoral thesis award competition finalist"],"prefix":"10.1109","author":[{"given":"Fabian","family":"Oboril","sequence":"first","affiliation":[]},{"given":"Mehdi B.","family":"Tahoori","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","first-page":"218","article-title":"NBTI Mitigation by NOP Assignment and Insertion","author":"firouzi","year":"2012","journal-title":"DATE"},{"doi-asserted-by":"publisher","key":"ref38","DOI":"10.1145\/1594233.1594264"},{"doi-asserted-by":"publisher","key":"ref33","DOI":"10.1109\/ISCAS.2015.7169182"},{"doi-asserted-by":"publisher","key":"ref32","DOI":"10.1109\/DAC.2002.1012674"},{"year":"2012","author":"hennessy","journal-title":"Computer Architecture A Quantitative Approach","key":"ref31"},{"doi-asserted-by":"publisher","key":"ref30","DOI":"10.1109\/MM.2012.23"},{"doi-asserted-by":"publisher","key":"ref37","DOI":"10.1145\/1785481.1785498"},{"doi-asserted-by":"publisher","key":"ref36","DOI":"10.1166\/jolpe.2013.1284"},{"doi-asserted-by":"publisher","key":"ref35","DOI":"10.1145\/2380445.2380514"},{"year":"0","journal-title":"OpenSPARC Overview","key":"ref34"},{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1145\/2039370.2039384"},{"key":"ref40","first-page":"1","article-title":"Exploiting Instruction Set Encoding for Aging-Aware Microprocessor Design","author":"oboril","year":"2016","journal-title":"ACM TODAES"},{"doi-asserted-by":"publisher","key":"ref11","DOI":"10.1109\/DSN.2012.6263957"},{"key":"ref12","first-page":"62","article-title":"ExtraTime: A Framework for Exploration of Clock and Power Gating for BTI and HCI Aging Mitigation","author":"oboril","year":"2011","journal-title":"ZuE"},{"key":"ref13","article-title":"ExtraTime: Eine Mikroarchitektur-Simulationsumgebung zur Modellierung, Analyse und Linderung von Alterungseffekten","author":"oboril","year":"2012","journal-title":"GMM MECHATRONIK"},{"doi-asserted-by":"publisher","key":"ref14","DOI":"10.1109\/MM.2006.82"},{"doi-asserted-by":"publisher","key":"ref15","DOI":"10.1145\/2445572.2445577"},{"doi-asserted-by":"publisher","key":"ref16","DOI":"10.1109\/TVLSI.2006.876103"},{"key":"ref17","first-page":"1","article-title":"High-Resolution Online Power Monitoring for Modern Microprocessors","author":"oboril","year":"2014","journal-title":"DATE"},{"year":"2015","author":"oboril","journal-title":"Cross-Layer Approaches for an Aging-Aware Design of Nanoscale Microprocessors","key":"ref18"},{"doi-asserted-by":"publisher","key":"ref19","DOI":"10.1007\/s10766-009-0104-y"},{"doi-asserted-by":"publisher","key":"ref28","DOI":"10.1109\/TCAD.2014.2298333"},{"doi-asserted-by":"publisher","key":"ref4","DOI":"10.1109\/MM.2005.110"},{"doi-asserted-by":"publisher","key":"ref27","DOI":"10.1109\/ICCAD.2013.6691098"},{"doi-asserted-by":"publisher","key":"ref3","DOI":"10.1145\/1941487.1941507"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.1109\/IRPS.2009.5173322"},{"doi-asserted-by":"publisher","key":"ref29","DOI":"10.1109\/TCAD.2012.2223467"},{"key":"ref5","first-page":"730","article-title":"Estimation of Statistical Variation in Temporal NBTI Degradation and its Impact on Lifetime Circuit Performance","author":"kang","year":"2007","journal-title":"ICCAD"},{"key":"ref8","article-title":"Is CMOS More Reliable with Scaling?","author":"mak","year":"0","journal-title":"Proc Int OnLine Testing Workshop"},{"key":"ref7","first-page":"1","article-title":"Workload dependent NBTI and PBTI Analysis for a sub-45nm Commercial Microprocessor","author":"mintamo","year":"0","journal-title":"IRPS"},{"key":"ref2","article-title":"Resiliency Challenges in Future Communications Infrastructure","author":"nguyen","year":"0","journal-title":"Comm Quality and Reliability Workshop 2014"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1109\/VTS.2007.22"},{"year":"2014","journal-title":"International Technology Roadmap for Semiconductors","key":"ref1"},{"doi-asserted-by":"publisher","key":"ref46","DOI":"10.1145\/1840845.1840898"},{"doi-asserted-by":"publisher","key":"ref20","DOI":"10.1109\/MM.2005.54"},{"doi-asserted-by":"publisher","key":"ref45","DOI":"10.1145\/1629911.1630039"},{"key":"ref48","first-page":"1","article-title":"On the Efficacy of NBTI Mitigation Techniques","author":"chan","year":"2011","journal-title":"DATE"},{"key":"ref22","article-title":"Olay: Combat the Signs of Aging with Introspective Reliability Management","author":"feng","year":"2008","journal-title":"Ann Arbor"},{"doi-asserted-by":"publisher","key":"ref47","DOI":"10.1109\/DATE.2009.5090637"},{"doi-asserted-by":"publisher","key":"ref21","DOI":"10.1109\/MICRO.2008.4771785"},{"doi-asserted-by":"publisher","key":"ref42","DOI":"10.1109\/VLSID.2007.129"},{"doi-asserted-by":"publisher","key":"ref24","DOI":"10.1145\/2206781.2206829"},{"doi-asserted-by":"publisher","key":"ref41","DOI":"10.1109\/ASPDAC.2014.6742891"},{"doi-asserted-by":"publisher","key":"ref23","DOI":"10.7873\/DATE.2013.068"},{"key":"ref44","first-page":"68","article-title":"Reducing Wearout in Embedded Processors using Proactive Fine-Grained Dynamic Runtime Adaptation","author":"oboril","year":"2012","journal-title":"ETS"},{"key":"ref26","first-page":"735","article-title":"An Efficient Method to Identify Critical Gates under Circuit Aging","author":"wang","year":"2007","journal-title":"ICCAD"},{"key":"ref43","first-page":"103","author":"gunadi","year":"2010","journal-title":"Combating Aging with the Colt Duty Cycle Equalizer in Micro"},{"doi-asserted-by":"publisher","key":"ref25","DOI":"10.1145\/2564926"}],"event":{"name":"2015 IEEE International Test Conference (ITC)","start":{"date-parts":[[2015,10,6]]},"location":"Anaheim, CA, USA","end":{"date-parts":[[2015,10,8]]}},"container-title":["2015 IEEE International Test Conference (ITC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7331771\/7342364\/07342422.pdf?arnumber=7342422","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,24]],"date-time":"2017-03-24T21:35:38Z","timestamp":1490391338000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7342422\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,10]]},"references-count":48,"URL":"https:\/\/doi.org\/10.1109\/test.2015.7342422","relation":{},"subject":[],"published":{"date-parts":[[2015,10]]}}}