{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,2]],"date-time":"2025-12-02T15:02:08Z","timestamp":1764687728340},"reference-count":24,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,11]]},"DOI":"10.1109\/test.2016.7805857","type":"proceedings-article","created":{"date-parts":[[2017,1,5]],"date-time":"2017-01-05T17:22:46Z","timestamp":1483636966000},"page":"1-10","source":"Crossref","is-referenced-by-count":6,"title":["Advanced test methodology for complex SoCs"],"prefix":"10.1109","author":[{"given":"Pavan","family":"Kumar Datla Jagannadha","sequence":"first","affiliation":[]},{"given":"Mahmut","family":"Yilmaz","sequence":"additional","affiliation":[]},{"given":"Milind","family":"Sonawane","sequence":"additional","affiliation":[]},{"given":"Sailendra","family":"Chadalavada","sequence":"additional","affiliation":[]},{"given":"Shantanu","family":"Sarangi","sequence":"additional","affiliation":[]},{"given":"Bonita","family":"Bhaskaran","sequence":"additional","affiliation":[]},{"given":"Ayub","family":"Abdollahian","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837366"},{"key":"ref11","article-title":"Hierarchical Implementation of the Sequential Compression (SeqPlus) Architecture to Achieve Concurrent Testing","author":"colburn","year":"2016","journal-title":"SNUG Synopsys"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2016.7477308"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2015.21"},{"key":"ref14","article-title":"Dynamic Clocking Architecture for Concurrent Testing and Peak Power Reduciton","author":"sonawane","year":"0","journal-title":"IEEE VLSI Test Symposium (VTS)"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2011.5783724"},{"key":"ref16","article-title":"Optimizing Test Time using a Scan Deserializer\/Serializer Architecture Enhanced for Large GPU Designs","author":"sonawane","year":"2012","journal-title":"SNUG"},{"key":"ref17","article-title":"A clock-gating based capture power droop reduction methodology for at-speed scan testing","author":"yang","year":"2007","journal-title":"DAT in Europe Conference & Exhibition (DATE)"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:20045139"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/VLSISOC.2006.313222"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2012.6231090"},{"journal-title":"The scan-DFT features of AMD's next-generation microprocessor core IEEE International Test Conference (ITC)","year":"2010","author":"yilmaz","key":"ref3"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2015.7116276"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2012.6401565"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2014.7035294"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.826558"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1271086"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.810737"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2432133"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2006.297694"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ICVD.2000.812650"},{"key":"ref21","article-title":"Low-power scan by partitioning and scan hold","author":"arvaniti","year":"2002","journal-title":"IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2016.7477310"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2016.7477289"}],"event":{"name":"2016 IEEE International Test Conference (ITC)","start":{"date-parts":[[2016,11,15]]},"location":"Fort Worth, TX, USA","end":{"date-parts":[[2016,11,17]]}},"container-title":["2016 IEEE International Test Conference (ITC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7794484\/7805805\/07805857.pdf?arnumber=7805857","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,1,21]],"date-time":"2017-01-21T00:09:20Z","timestamp":1484957360000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7805857\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,11]]},"references-count":24,"URL":"https:\/\/doi.org\/10.1109\/test.2016.7805857","relation":{},"subject":[],"published":{"date-parts":[[2016,11]]}}}