{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T15:14:20Z","timestamp":1730301260738,"version":"3.28.0"},"reference-count":18,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,11]]},"DOI":"10.1109\/test.2016.7805865","type":"proceedings-article","created":{"date-parts":[[2017,1,5]],"date-time":"2017-01-05T22:22:46Z","timestamp":1483654966000},"page":"1-10","source":"Crossref","is-referenced-by-count":1,"title":["An on-chip self-test architecture with test patterns recorded in scan chains"],"prefix":"10.1109","author":[{"given":"Kuen-Jong","family":"Lee","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pin-Hao","family":"Tang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael A.","family":"Kochte","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2001.990304"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.831593"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1023\/A:1012283800306"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2009.43"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2009.26"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/1403375.1403590"},{"year":"0","author":"bush","key":"ref16"},{"year":"0","key":"ref17"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2008.4700553"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/288548.288563"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2006.105"},{"key":"ref6","article-title":"Code Based Test Data Compression for SoC Testing: Optimization of Time","author":"mehta","year":"2012","journal-title":"Power and Area Overhead"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.826558"},{"key":"ref8","first-page":"237","article-title":"LFSR-coded test pattern for scan designs","author":"koenemann","year":"1991","journal-title":"Proc Eur Test Conf"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2006.297643"},{"key":"ref2","article-title":"System-on-Chip Test Architectures: Nanometer Design for Testability","volume":"2","author":"wang","year":"2010"},{"key":"ref1","volume":"5","author":"wang","year":"2006","journal-title":"VLSI Test Principles and Architectures Design for Testability"},{"key":"ref9","first-page":"120","article-title":"Generation of vector patterns through reseeding of multiple polynomial linear feedback shift register","author":"hellebrand","year":"1992","journal-title":"Proc Int'l Test Conf"}],"event":{"name":"2016 IEEE International Test Conference (ITC)","start":{"date-parts":[[2016,11,15]]},"location":"Fort Worth, TX, USA","end":{"date-parts":[[2016,11,17]]}},"container-title":["2016 IEEE International Test Conference (ITC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7794484\/7805805\/07805865.pdf?arnumber=7805865","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,1,21]],"date-time":"2017-01-21T04:45:55Z","timestamp":1484973955000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7805865\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,11]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/test.2016.7805865","relation":{},"subject":[],"published":{"date-parts":[[2016,11]]}}}