{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T11:44:12Z","timestamp":1725795852828},"reference-count":25,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,10]]},"DOI":"10.1109\/test.2017.8242036","type":"proceedings-article","created":{"date-parts":[[2018,1,1]],"date-time":"2018-01-01T16:33:50Z","timestamp":1514824430000},"page":"1-9","source":"Crossref","is-referenced-by-count":11,"title":["Full-scan LBIST with capture-per-cycle hybrid test points"],"prefix":"10.1109","author":[{"given":"Sylwester","family":"Milewski","sequence":"first","affiliation":[]},{"given":"Nilanjan","family":"Mukherjee","sequence":"additional","affiliation":[]},{"given":"Janusz","family":"Rajski","sequence":"additional","affiliation":[]},{"given":"Jedrzej","family":"Solecki","sequence":"additional","affiliation":[]},{"given":"Jerzy","family":"Tyszer","sequence":"additional","affiliation":[]},{"given":"Justyna","family":"Zawada","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.1999.810763"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2002.996747"},{"key":"ref12","first-page":"37","article-title":"Built-in logic block observation techniques","author":"konemann","year":"1979","journal-title":"Proc ITC"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/43.21818"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2013.45"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2016.7805826"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2608984"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.1997.643983"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/OLT.2001.937825"},{"key":"ref19","first-page":"104","article-title":"Virtual compression through test vector stitching for scan based designs","author":"rao","year":"2003","journal-title":"Proc DATE"},{"key":"ref4","article-title":"Simultaneous self-testing system","author":"bardell","year":"1985","journal-title":"US patent 4513418"},{"key":"ref3","first-page":"359","article-title":"Progressive random access scan: a simultaneous solution to test power, test data volume and test time","author":"baik","year":"2005","journal-title":"Proc ITC"},{"key":"ref6","first-page":"658","article-title":"A novel combinational testability analysis by considering signal correlation","author":"chang","year":"1998","journal-title":"Proc ITC"},{"key":"ref5","first-page":"705","article-title":"Applications oftestabil-ity analysis: from ATPG to critical delay path tracing","author":"brglez","year":"1984","journal-title":"Proc ITC"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041754"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1994.528044"},{"key":"ref2","first-page":"50","article-title":"Testing VLSI with random access scan","author":"ando","year":"1980","journal-title":"Proc Compcon"},{"key":"ref9","first-page":"501","article-title":"Synthesis of pseudorandom pattern testable designs","author":"iyengar","year":"1989","journal-title":"Proc ITC"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2015.7342383"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.844111"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:20020158"},{"key":"ref21","first-page":"253","article-title":"Test point insertion for scan-based BIST","author":"seiss","year":"1991","journal-title":"Proc ETC"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2003.1223640"},{"key":"ref23","first-page":"3","article-title":"An automated BIST approach for general se-quential logic synthesis","author":"stroud","year":"1988","journal-title":"Proc DAC"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2016.7805828"}],"event":{"name":"2017 IEEE International Test Conference (ITC)","start":{"date-parts":[[2017,10,31]]},"location":"Fort Worth, TX","end":{"date-parts":[[2017,11,2]]}},"container-title":["2017 IEEE International Test Conference (ITC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8227522\/8242015\/08242036.pdf?arnumber=8242036","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,2,5]],"date-time":"2018-02-05T17:35:20Z","timestamp":1517852120000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8242036\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,10]]},"references-count":25,"URL":"https:\/\/doi.org\/10.1109\/test.2017.8242036","relation":{},"subject":[],"published":{"date-parts":[[2017,10]]}}}