{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T04:06:59Z","timestamp":1725682019306},"reference-count":18,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,10]]},"DOI":"10.1109\/test.2017.8242038","type":"proceedings-article","created":{"date-parts":[[2018,1,1]],"date-time":"2018-01-01T16:33:50Z","timestamp":1514824430000},"page":"1-10","source":"Crossref","is-referenced-by-count":5,"title":["RTL functional test generation using factored concolic execution"],"prefix":"10.1109","author":[{"given":"Sonal","family":"Pinto","sequence":"first","affiliation":[]},{"given":"Michael S.","family":"Hsiao","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/1065010.1065036"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2012.6401556"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2015.7116286"},{"key":"ref13","first-page":"104","article-title":"Scalable Test Generation by Interleaving Concrete and Symbolic Execution","author":"xiaoke","year":"2014","journal-title":"International Conference on VLSI Design and International Conference on Embedded Systems"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/EDAC.1991.206393"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2015.7138737"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2481863"},{"journal-title":"Z3 Theorem Prover","year":"0","key":"ref17"},{"journal-title":"Verilator","year":"0","author":"snyder","key":"ref18"},{"key":"ref4","first-page":"209","article-title":"KLEE: unassisted and automatic generation of high-coverage tests for complex systems programs","author":"dunbar","year":"2008","journal-title":"Proc of the 8th USENIX Conference on Operating Systems Design and Implementation"},{"key":"ref3","article-title":"IWLS 2005 Benchmarks","author":"albrecht","year":"2005","journal-title":"International Workshop on Logic Synthesis"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/390013.808479"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/54.867894"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/HLDVT.2009.5340179"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1081706.1081750"},{"journal-title":"Software Testing Techniques","year":"1990","author":"beizer","key":"ref2"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/378239.378278"},{"key":"ref9","first-page":"1","article-title":"Efficient validation input generation in RTL by hybridized source code analysis","author":"liu","year":"2011","journal-title":"Design Automation and Test in Europe"}],"event":{"name":"2017 IEEE International Test Conference (ITC)","start":{"date-parts":[[2017,10,31]]},"location":"Fort Worth, TX","end":{"date-parts":[[2017,11,2]]}},"container-title":["2017 IEEE International Test Conference (ITC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8227522\/8242015\/08242038.pdf?arnumber=8242038","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,2,5]],"date-time":"2018-02-05T17:35:18Z","timestamp":1517852118000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8242038\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,10]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/test.2017.8242038","relation":{},"subject":[],"published":{"date-parts":[[2017,10]]}}}