{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T10:26:32Z","timestamp":1725704792563},"reference-count":36,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,10]]},"DOI":"10.1109\/test.2017.8242055","type":"proceedings-article","created":{"date-parts":[[2018,1,1]],"date-time":"2018-01-01T16:33:50Z","timestamp":1514824430000},"page":"1-8","source":"Crossref","is-referenced-by-count":6,"title":["Analysis and mitigation or IR-Drop induced scan shift-errors"],"prefix":"10.1109","author":[{"given":"Stefan","family":"Holst","sequence":"first","affiliation":[]},{"given":"Eric","family":"Schneider","sequence":"additional","affiliation":[]},{"given":"Koshi","family":"Kawagoe","sequence":"additional","affiliation":[]},{"given":"Michael A.","family":"Kochte","sequence":"additional","affiliation":[]},{"given":"Kohei","family":"Miyase","sequence":"additional","affiliation":[]},{"given":"Hans-Joachim","family":"Wunderlich","sequence":"additional","affiliation":[]},{"given":"Seiji","family":"Kajihara","sequence":"additional","affiliation":[]},{"given":"Xiaoqing","family":"Wen","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1996.569803"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2016.49"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2014.7001324"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/2714564"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/MSE.2009.5270840"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2009.43"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2007.4437611"},{"journal-title":"Electronic Design Automation Synthesis Verification and Test","year":"2008","author":"wang","key":"ref10"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2011.5783776"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2007.378781"},{"key":"ref13","first-page":"369","article-title":"DFT of the Cell Processor and its Impact on EDA Test Software","author":"bushard","year":"2006","journal-title":"Proc IEEE Asian Test Symp"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1147\/rd.466.0649"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1023\/A:1008383013319"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/54.2032"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2030445"},{"journal-title":"Power-Aware Testing and Test Strategies for Low Power Devices","year":"2009","author":"girard","key":"ref18"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2011.6139162"},{"key":"ref28","first-page":"533","article-title":"Transition delay fault test pattern generation considering supply voltage noise in a SOC design","author":"ahmed","year":"2007","journal-title":"Proc ACM\/IEEE Design Automation Conf"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1271098"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2012.6401549"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/DTIS.2006.1708693"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2008.4700659"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2007.79"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2015.25"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1998.672552"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2442087.2442102"},{"journal-title":"VLSI Test Principles and Architectures Design for Testability (Systems on Silicon)","year":"2006","author":"wang","key":"ref2"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/4.881198"},{"journal-title":"Essentials of Electronic Testing for Digital Memory and Mixed-Signal VLSI Circuits","year":"2000","author":"bushnell","key":"ref1"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2002.1011127"},{"key":"ref22","first-page":"265","article-title":"On low-capture-power test generation for scan testing","author":"wen","year":"2005","journal-title":"Proc IEEE VLSI Test Symp"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.2000.843824"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2016.7477289"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2228741"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2001.923456"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2002.1181690"}],"event":{"name":"2017 IEEE International Test Conference (ITC)","start":{"date-parts":[[2017,10,31]]},"location":"Fort Worth, TX","end":{"date-parts":[[2017,11,2]]}},"container-title":["2017 IEEE International Test Conference (ITC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8227522\/8242015\/08242055.pdf?arnumber=8242055","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,2,5]],"date-time":"2018-02-05T17:35:13Z","timestamp":1517852113000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8242055\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,10]]},"references-count":36,"URL":"https:\/\/doi.org\/10.1109\/test.2017.8242055","relation":{},"subject":[],"published":{"date-parts":[[2017,10]]}}}