{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T15:14:30Z","timestamp":1730301270098,"version":"3.28.0"},"reference-count":20,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,10]]},"DOI":"10.1109\/test.2017.8242070","type":"proceedings-article","created":{"date-parts":[[2018,1,1]],"date-time":"2018-01-01T21:33:50Z","timestamp":1514842430000},"page":"1-10","source":"Crossref","is-referenced-by-count":4,"title":["Marginal PCB assembly defect detection on DDR3\/4 memory bus"],"prefix":"10.1109","author":[{"given":"Sergei","family":"Odintsov","sequence":"first","affiliation":[]},{"given":"Artur","family":"Jutman","sequence":"additional","affiliation":[]},{"given":"Sergei","family":"Devadze","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","first-page":"121","article-title":"Comparison of off-chip interconnect validation to field failures","author":"blankenbeckler","year":"2011","journal-title":"VALID 2011 The Third International Conference on Advances in System Testing and Validation Lifecycle"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/IMPACT.2014.7048403"},{"key":"ref12","first-page":"180","article-title":"The effects of defects on high-speed boards","author":"parker","year":"2009","journal-title":"IEEE International Test Conference 2005"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2009.5355667"},{"key":"ref14","article-title":"System Marginality Validation of DDR3\/DDR4 Memory and Serial I\/O","author":"al","year":"2014","journal-title":"ASSET InterTech"},{"journal-title":"ASSET InterTech","article-title":"Scanworks &#x00AE; Intel &#x00AE; IBIST Xeon 5600 DDR3 Memory Test","year":"2012","key":"ref15"},{"journal-title":"An Engineer's Guide to Automated Testing of High-Speed Interfaces","year":"2010","author":"moreira","key":"ref16"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2011.14"},{"journal-title":"High-Speed Digital System Design a Handbook of Interconnect Theory and Design Practices","year":"2000","author":"hall","key":"ref18"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2016.7805829"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2004.1386948"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2432142"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2016.7519295"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2009.5355673"},{"journal-title":"JEDEC JESD79-4B","year":"2017","key":"ref8"},{"journal-title":"Published by","year":"2000","key":"ref7"},{"key":"ref2","first-page":"529","article-title":"Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores","volume":"18","author":"chen","year":"2002","journal-title":"2004 International Conferce on Test"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1992.527840"},{"journal-title":"JEDEC JESD79-3F","year":"2012","key":"ref9"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2006.297691"}],"event":{"name":"2017 IEEE International Test Conference (ITC)","start":{"date-parts":[[2017,10,31]]},"location":"Fort Worth, TX","end":{"date-parts":[[2017,11,2]]}},"container-title":["2017 IEEE International Test Conference (ITC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8227522\/8242015\/08242070.pdf?arnumber=8242070","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,2,5]],"date-time":"2018-02-05T22:35:17Z","timestamp":1517870117000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8242070\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,10]]},"references-count":20,"URL":"https:\/\/doi.org\/10.1109\/test.2017.8242070","relation":{},"subject":[],"published":{"date-parts":[[2017,10]]}}}