{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T10:48:30Z","timestamp":1761648510290,"version":"3.28.0"},"reference-count":34,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,10]]},"DOI":"10.1109\/test.2017.8242082","type":"proceedings-article","created":{"date-parts":[[2018,1,1]],"date-time":"2018-01-01T21:33:50Z","timestamp":1514842430000},"page":"1-10","source":"Crossref","is-referenced-by-count":2,"title":["Design-for-test and test time optimization for 3D SOCs"],"prefix":"10.1109","author":[{"given":"Surajit Kumar","family":"Roy","sequence":"first","affiliation":[]},{"given":"Chandan","family":"Giri","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ASQED.2013.6643579"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228545"},{"key":"ref31","first-page":"848853","article-title":"Architecture of Ring-based Redundant TSV for Clustered Faults","author":"lo","year":"2015","journal-title":"Proc Design Automation and Test in Europe"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2011.37"},{"key":"ref34","first-page":"106","article-title":"Recovery of Faulty TSVs in 3D SOC","author":"roy","year":"2015","journal-title":"Proc ISQED"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/VLSISOC.2007.4402522"},{"key":"ref11","first-page":"122","article-title":"Session Based Core Test Tcheduling for 3D SOCs","author":"roy","year":"2014","journal-title":"Proc IEEE Computer Soc Annu Symp VLSI (ISVLSI)"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2010.06.015"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090661"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2160410"},{"key":"ref15","first-page":"67","article-title":"Resource-constrained system-on-chip test: A survey","volume":"15","author":"xuand","year":"2005","journal-title":"IEEE Proceedings Computers and Digital Techniques"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2160177"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2014.6818764"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2015.7116268"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-011-5233-8"},{"key":"ref28","doi-asserted-by":"crossref","first-page":"111","DOI":"10.1109\/JSSC.2009.2034408","article-title":"8 Gb 3-D DDR3 DRAM Using Through- Silicon-Via Technology","volume":"45","author":"uksong","year":"2010","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt.2009.0111"},{"key":"ref27","first-page":"387","article-title":"Diagnostic Tests for Pre-Bond TSV Defects","author":"zhang","year":"2014","journal-title":"Proc of IEEE International Conference on VLSI Design"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/APCCAS.2010.5775087"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/IEEESTD.2005.96465"},{"key":"ref29","first-page":"166171","article-title":"TSV,&#x201C; Redundancy: Architecture and Design Issues in 3D IC","author":"hsieh","year":"2010","journal-title":"Proc of DATE"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1023\/A:1014916913577"},{"key":"ref8","first-page":"74","article-title":"Optimal Core Wrapper Width Selection and SOC Test Scheduling based on 3D Bin Packing Algorithm","author":"huang","year":"2002","journal-title":"Proc of ITC"},{"key":"ref7","first-page":"685","article-title":"Wrapper\/TAM Coop-timization, Constraint-driven Test Scheduling, and Tester Data Volume Reduction for SOCs","author":"iyengar","year":"2002","journal-title":"Proc of DAC"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/1148015.1148016"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/s11390-013-1316-6"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.136"},{"key":"ref20","doi-asserted-by":"crossref","first-page":"268","DOI":"10.1049\/iet-cdt.2014.0137","article-title":"Optimization of Test Architecture in 3D Stacked ICs for Partial Stack\/Complete Stack using Hard SOCs","volume":"9","author":"roy","year":"2015","journal-title":"IET Computers and Digital Techniques"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ISED.2012.49"},{"key":"ref21","first-page":"1","article-title":"Optimization of Test Architecture in 3D stacked IC for Partial stack\/Complete Stack using Hard Die","author":"roy","year":"2013","journal-title":"Proc of IDT"},{"key":"ref24","article-title":"Electrical Tests for Three-dimensional ICs (3DICs) with TSVs","author":"chen","year":"2010","journal-title":"Proc 3DTest Workshop Informal Digest"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ISED.2012.49"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2011.57"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2011.6139179"}],"event":{"name":"2017 IEEE International Test Conference (ITC)","start":{"date-parts":[[2017,10,31]]},"location":"Fort Worth, TX","end":{"date-parts":[[2017,11,2]]}},"container-title":["2017 IEEE International Test Conference (ITC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8227522\/8242015\/08242082.pdf?arnumber=8242082","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,25]],"date-time":"2022-01-25T21:55:00Z","timestamp":1643147700000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8242082\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,10]]},"references-count":34,"URL":"https:\/\/doi.org\/10.1109\/test.2017.8242082","relation":{},"subject":[],"published":{"date-parts":[[2017,10]]}}}