{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T15:14:46Z","timestamp":1730301286519,"version":"3.28.0"},"reference-count":39,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,10]]},"DOI":"10.1109\/test.2018.8624794","type":"proceedings-article","created":{"date-parts":[[2019,1,25]],"date-time":"2019-01-25T03:09:16Z","timestamp":1548385756000},"page":"1-10","source":"Crossref","is-referenced-by-count":2,"title":["Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation"],"prefix":"10.1109","author":[{"given":"Francisco E.","family":"Rangel-Patino","sequence":"first","affiliation":[]},{"given":"Jose E.","family":"Rayas-Sanchez","sequence":"additional","affiliation":[]},{"given":"Nagib","family":"Hakim","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation PhD Thesis Dept of Electronics Systems and Informatics ITESO Tlaquepaque Mexico","year":"2018","author":"rangel-patino","key":"ref39"},{"journal-title":"Serial Advanced Technology Attachment 3 2 Specification","year":"2016","key":"ref38"},{"key":"ref33","first-page":"1","article-title":"High-speed links receiver optimization in post-silicon validation exploiting Broyden-based input space mapping","author":"rangel-pati\u00f1o","year":"2018","journal-title":"IEEE MTT-S Int Conf Num EM Mutiphys Model Opt RF Microw Terahertz App (NEMO-2018)"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1016\/0041-5553(67)90144-9"},{"key":"ref31","first-page":"1","article-title":"Design of discrete-value passive harmonic filters using sequential neural-network approximation and orthogonal array","author":"chang","year":"2005","journal-title":"IEEE Trans Dist Conf Expo Asia Pacific"},{"journal-title":"Experiments Planning Analysis and Parameter Design Optimization New York NY","year":"2000","author":"wu","key":"ref30"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1007\/BF01197708"},{"key":"ref36","first-page":"540","article-title":"Eye diagram system margining surrogate-based optimization in a server silicon validation platform","author":"rangel-patino","year":"2017","journal-title":"European Microw Conf (EuMC-2017)"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/MMM.2015.2514188"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/22.475649"},{"journal-title":"Universal Serial Bus Revision 3 1 Specification","year":"2016","key":"ref10"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2017.2701368"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1214\/ss\/1177012413"},{"key":"ref13","article-title":"Aspects of the Matlab toolbox DACE","author":"lophaven","year":"2002","journal-title":"Internal Report IMM-TR-2002&#x2013;13 Technical University of Denmark Lyngby"},{"journal-title":"Understanding Eye Pattern Measurements application note no 11410-00533","year":"2010","key":"ref14"},{"journal-title":"Standard for Ethernet IEEE Standard 802 3-2015","year":"0","key":"ref15"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1016\/j.aeue.2014.07.019"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2013.6572277"},{"key":"ref18","first-page":"1321","article-title":"Optimization of FIR filter to improve eye diagram for general transmission line systems","author":"cheng","year":"2010","journal-title":"Proc Design Automation Test Europe Conf Exhibition"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ICCDCS.2017.7959697"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2006.885902"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/4.938367"},{"journal-title":"Neural Space Mapping Methods for Modeling and Design of Microw Circuits Ph D Thesis Dept of Electrical and Comp Eng McMaster University Hamilton Canada","year":"2001","author":"rayas-s\u00e1nchez","key":"ref27"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687534"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/LAMC.2016.7851268"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1162\/neco.1992.4.3.415"},{"key":"ref5","first-page":"161","author":"miller","year":"2003","journal-title":"D in Proc Int Great Lakes Symp on VLSI Washington C"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2014.6818767"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429502"},{"key":"ref2","article-title":"A holistic formulation for system margining and jitter tolerance optimization in industrial post-silicon validation","volume":"6","author":"rangel-pati\u00f1o","year":"2018","journal-title":"IEEE Transactions on Emerging Topics in Computing"},{"key":"ref9","first-page":"360","article-title":"Accelerating jitter tolerance qualification for high speed serial interfaces","author":"fan","year":"2009","journal-title":"in IEEE Int Symp on Quality Electronic Design San Jose CA"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837278"},{"journal-title":"Introduction to PCI Express A Hardw and Softw Developer's Guide Hillsboro OR Intel Press","year":"2003","author":"wilen","key":"ref20"},{"key":"ref22","first-page":"1","article-title":"Direct optimization of a PCI Express link equalization in industrial post-silicon validation","author":"rangel-pati\u00f1o","year":"2018","journal-title":"IEEE Latin American Test Symp (LATS 2018) Sao Paulo Brazil"},{"journal-title":"PCI Express Base Specification Revision 4 0 Version 1 0","year":"2017","key":"ref21"},{"journal-title":"Open-source Software for Mathematics Science and Engineering","year":"2017","key":"ref24"},{"journal-title":"High Speed SERDES Devices and Applications New York NY","year":"2008","author":"stauffer","key":"ref23"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1016\/0893-6080(89)90020-8"},{"key":"ref25","article-title":"Post-silicon receiver equalization metamodeling by artificial neural networks","volume":"37","author":"rangel-pati\u00f1o","year":"2018","journal-title":"IEEE Trans Computer-Aided Design of Integrated Circuits and Systems"}],"event":{"name":"2018 IEEE International Test Conference (ITC)","start":{"date-parts":[[2018,10,29]]},"location":"Phoenix, AZ, USA","end":{"date-parts":[[2018,11,1]]}},"container-title":["2018 IEEE International Test Conference (ITC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8610502\/8624670\/08624794.pdf?arnumber=8624794","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,27]],"date-time":"2022-01-27T00:05:09Z","timestamp":1643241909000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8624794\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,10]]},"references-count":39,"URL":"https:\/\/doi.org\/10.1109\/test.2018.8624794","relation":{},"subject":[],"published":{"date-parts":[[2018,10]]}}}