{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T15:14:54Z","timestamp":1730301294492,"version":"3.28.0"},"reference-count":32,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,10]]},"DOI":"10.1109\/test.2018.8624896","type":"proceedings-article","created":{"date-parts":[[2019,1,25]],"date-time":"2019-01-25T03:09:16Z","timestamp":1548385756000},"page":"1-10","source":"Crossref","is-referenced-by-count":4,"title":["Test of Supply Noise for Emerging Non-Volatile Memory"],"prefix":"10.1109","author":[{"given":"Mohammad Nasim Imtiaz","family":"Khan","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Swaroop","family":"Ghosh","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"year":"0","key":"ref32","article-title":"Test time"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2014.2358998"},{"key":"ref30","article-title":"Current Compliant Sensing Architecture For Multilevel Phase Change Memory","author":"happ","year":"2007","journal-title":"US 11\/620 432"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2016.2591554"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2016.7805834"},{"key":"ref12","first-page":"54","article-title":"STTRAM scaling and retention failure","volume":"17","author":"naeimi","year":"2013"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2820508"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927073"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2018.8368632"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2016.2536258"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2029114"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2161785"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2013.2253329"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/IITC.2007.382360"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2004.825805"},{"first-page":"3","article-title":"Wire Capacitance and Resistance Calculator for 65nm","year":"2008","key":"ref27"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/SNW.2012.6243331"},{"first-page":"3","article-title":"16Mb 256K x 16 MRAM Memory-Everspin","year":"2015","key":"ref6"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2009.5280845"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISAF.2008.4693959"},{"year":"0","key":"ref8","article-title":"Intel Optane Memory Series"},{"year":"2016","key":"ref7","article-title":"RM24C256DS, 256-Kbit 1.65V Minimum Non-volatile Serial EEPROM I2C Bus"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2010.5703349"},{"year":"0","key":"ref9","article-title":"FM28V102A 1-Mbit (64 K x 16) F-RAM Memory"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2011.5993623"},{"key":"ref20","first-page":"262","article-title":"Droop mitigating last level cache architecture for STTRAM","author":"aluru","year":"2017","journal-title":"Proceedings of the Conference on Design Automation and Test in Europe DATE '10 (3001 Leuven Belgium Belgium)"},{"key":"ref22","first-page":"6","article-title":"Information Leakage Attacks on Emerging Non-Volatile Memory and Countermeasures","author":"khan","year":"2018","journal-title":"In Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED '18)"},{"key":"ref21","doi-asserted-by":"crossref","DOI":"10.1145\/3214292.3214302","article-title":"Fault injection attacks on emerging nonvolatile memory and countermeasures","author":"khan","year":"2018","journal-title":"In Proceedings of the 7th International Workshop on Hardware and Architectural Support for Security and Privacy (HASP '18)"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2015.2492421"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2018.00021"},{"year":"2005","key":"ref26","article-title":"Interconnect: Capacitance and Resistance for 65nm technology"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2016.7477293"}],"event":{"name":"2018 IEEE International Test Conference (ITC)","start":{"date-parts":[[2018,10,29]]},"location":"Phoenix, AZ, USA","end":{"date-parts":[[2018,11,1]]}},"container-title":["2018 IEEE International Test Conference (ITC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8610502\/8624670\/08624896.pdf?arnumber=8624896","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,26]],"date-time":"2022-01-26T23:58:58Z","timestamp":1643241538000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8624896\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,10]]},"references-count":32,"URL":"https:\/\/doi.org\/10.1109\/test.2018.8624896","relation":{},"subject":[],"published":{"date-parts":[[2018,10]]}}}