{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,11]],"date-time":"2025-04-11T08:50:17Z","timestamp":1744361417541,"version":"3.37.3"},"reference-count":19,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2018,4,1]],"date-time":"2018-04-01T00:00:00Z","timestamp":1522540800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Emerg. Topics Comput."],"published-print":{"date-parts":[[2018,4,1]]},"DOI":"10.1109\/tetc.2016.2582732","type":"journal-article","created":{"date-parts":[[2016,6,29]],"date-time":"2016-06-29T22:22:59Z","timestamp":1467238979000},"page":"200-206","source":"Crossref","is-referenced-by-count":3,"title":["A Low-Power Frequency Multiplier for Multi-GHz Applications"],"prefix":"10.1109","volume":"6","author":[{"given":"Andreas","family":"Tsimpos","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andreas Christos","family":"Demartinos","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2687-0285","authenticated-orcid":false,"given":"Spyridon","family":"Vlassis","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"George","family":"Souliotis","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","first-page":"419","article-title":"A CMOS delay-locked loop based frequency\n multiplier for wide-range operation","author":"weng","year":"0","journal-title":"Proc IEEE Conf Electron Devices Solid-State Circuits"},{"key":"ref11","doi-asserted-by":"crossref","first-page":"1205","DOI":"10.1109\/TCSII.2006.883103","article-title":"A\n low-phase noise, anti-harmonic programmable DLL frequency multiplier with period error compensation for spur reduction","volume":"53","author":"qingjin","year":"2006","journal-title":"IEEE Trans Circuits Systems II Exp Briefs"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/SOCDC.2009.5423833"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2019757"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1007\/s10470-015-0495-1"},{"key":"ref15","doi-asserted-by":"crossref","first-page":"401","DOI":"10.1109\/JSSC.2015.2496781","article-title":"A low-jitter and fractional-resolution injection-locked\n clock multiplier using a DLL-based real-time PVT calibrator with replica-delay cells","volume":"51","author":"kim","year":"2016","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/DTIS.2015.7127354"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/4.508209"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2028927"},{"key":"ref19","first-page":"1","article-title":"A 3 GHz VCO suitable for MIPI M-PHY serial interface","author":"demartinos","year":"0","journal-title":"Proc 10th IEEE Int Conf Des Technol Integr Syst Nanoscale Era"},{"year":"0","key":"ref4"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757506"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2013.04.004"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2014.6865183"},{"key":"ref8","first-page":"1174","article-title":"A 2 GHz fully differential\n DLL-based frequency multiplier for high speed serial link circuit","volume":"2","author":"cheng","year":"0","journal-title":"Proc IEEE Int Symp Circuits Syst"},{"key":"ref7","first-page":"790","article-title":"A 2.64 GHz wide range low power DLL-based frequency multiplier with CML circuits using adaptive\n body bias","author":"lin","year":"0","journal-title":"Proc IEEE Int Conf Electron Circuits and Syst"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"273","DOI":"10.1109\/30.964109","article-title":"A 1.0 Gb\/s BiCMOS multi-channel optical\n interface transmitter and receiver chip set for high resolution digital displays","volume":"47","author":"lee","year":"2001","journal-title":"IEEE Int Conf Consumer Electronics"},{"journal-title":"Design of Integrated Circuits for Optical Communications","year":"2003","author":"razavi","key":"ref1"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/4.890315"}],"container-title":["IEEE Transactions on Emerging Topics in Computing"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6245516\/8372818\/07501798.pdf?arnumber=7501798","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:25:55Z","timestamp":1642004755000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/7501798\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,4,1]]},"references-count":19,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tetc.2016.2582732","relation":{},"ISSN":["2168-6750"],"issn-type":[{"type":"electronic","value":"2168-6750"}],"subject":[],"published":{"date-parts":[[2018,4,1]]}}}