{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T20:32:05Z","timestamp":1740169925884,"version":"3.37.3"},"reference-count":33,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2018,10,1]],"date-time":"2018-10-01T00:00:00Z","timestamp":1538352000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Emerg. Topics Comput."],"published-print":{"date-parts":[[2018,10,1]]},"DOI":"10.1109\/tetc.2016.2593628","type":"journal-article","created":{"date-parts":[[2016,7,22]],"date-time":"2016-07-22T18:32:50Z","timestamp":1469212370000},"page":"460-473","source":"Crossref","is-referenced-by-count":5,"title":["Clock-Less DFT-Less Test Strategy for Null Convention Logic"],"prefix":"10.1109","volume":"6","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-0682-396X","authenticated-orcid":false,"given":"Nastaran","family":"Nemati","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8401-5477","authenticated-orcid":false,"given":"Paul","family":"Beckett","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mark C.","family":"Reed","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Karl","family":"Fant","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"ref33","DOI":"10.1109\/ASYNC.2012.14"},{"year":"2012","journal-title":"Arizona State University Tempe AZ USA","key":"ref32"},{"doi-asserted-by":"publisher","key":"ref31","DOI":"10.1109\/EWDTS.2010.5742076"},{"year":"2005","author":"kabisatpathy","journal-title":"Fault Diagnosis of Analog Integrated Circuits","key":"ref30"},{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1109\/ISCAS.2014.6865492"},{"doi-asserted-by":"publisher","key":"ref11","DOI":"10.1109\/DSN.2004.1311875"},{"doi-asserted-by":"publisher","key":"ref12","DOI":"10.2200\/S00202ED1V01Y200907DCS023"},{"key":"ref13","first-page":"102","article-title":"Some faults need an IDDQ test","author":"makar","year":"0","journal-title":"Proc IEEE Int Workshop IDDQ Testing"},{"key":"ref14","volume":"17","author":"bushnell","year":"2000","journal-title":"Essentials of Electronic Testing for Digital Memory and Mixed-Signal VLSI Circuits"},{"doi-asserted-by":"publisher","key":"ref15","DOI":"10.1109\/TEST.1995.529895"},{"doi-asserted-by":"publisher","key":"ref16","DOI":"10.1109\/TEST.1994.527983"},{"doi-asserted-by":"publisher","key":"ref17","DOI":"10.1109\/MDT.2002.1033787"},{"year":"2013","author":"jarrige","article-title":"Quiescent current (IDDQ) indication and testing apparatus and methods","key":"ref18"},{"year":"2015","author":"xu","article-title":"On-chip current test circuit","key":"ref19"},{"doi-asserted-by":"publisher","key":"ref28","DOI":"10.1007\/978-1-4419-7548-5"},{"doi-asserted-by":"publisher","key":"ref4","DOI":"10.1109\/MM.2007.28"},{"doi-asserted-by":"publisher","key":"ref27","DOI":"10.1109\/ISCAS.2016.7527348"},{"doi-asserted-by":"publisher","key":"ref3","DOI":"10.1109\/JPROC.2009.2035449"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.1002\/0471702897"},{"doi-asserted-by":"publisher","key":"ref29","DOI":"10.1109\/TEST.1996.556963"},{"doi-asserted-by":"publisher","key":"ref5","DOI":"10.1109\/TVLSI.2009.2013470"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1007\/s10836-008-5083-1"},{"key":"ref7","first-page":"171","article-title":"Testing of\n asynchronous designs by &#x201C;inappropriate","author":"kondratyev","year":"0","journal-title":"Proc IEEE Int Symp Asynchronous Circuits Syst"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1109\/MSPEC.2012.6247562"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1007\/s10836-011-5195-x"},{"doi-asserted-by":"publisher","key":"ref1","DOI":"10.1109\/MDT.2011.110"},{"doi-asserted-by":"publisher","key":"ref20","DOI":"10.1109\/5.843000"},{"year":"2015","author":"narayen","article-title":"System and method for compensating measured IDDQ values","key":"ref22"},{"doi-asserted-by":"publisher","key":"ref21","DOI":"10.4236\/cs.2011.23020"},{"key":"ref24","first-page":"454","article-title":"Process-variation-aware IDDQ diagnois for nano-scale CMOS designs&#x2014;The first step","author":"chang","year":"0","journal-title":"Proc Des Autom Test Europe Conf Exhibition"},{"doi-asserted-by":"publisher","key":"ref23","DOI":"10.1016\/S0167-9260(02)00023-8"},{"doi-asserted-by":"publisher","key":"ref26","DOI":"10.1109\/ASPDAC.2013.6509666"},{"doi-asserted-by":"publisher","key":"ref25","DOI":"10.1109\/TVLSI.2014.2326081"}],"container-title":["IEEE Transactions on Emerging Topics in Computing"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6245516\/8558622\/07519054.pdf?arnumber=7519054","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,27]],"date-time":"2022-01-27T03:45:18Z","timestamp":1643255118000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/7519054\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,10,1]]},"references-count":33,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tetc.2016.2593628","relation":{},"ISSN":["2168-6750","2376-4562"],"issn-type":[{"type":"electronic","value":"2168-6750"},{"type":"electronic","value":"2376-4562"}],"subject":[],"published":{"date-parts":[[2018,10,1]]}}}