{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T20:32:11Z","timestamp":1740169931864,"version":"3.37.3"},"reference-count":47,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2020,4,1]],"date-time":"2020-04-01T00:00:00Z","timestamp":1585699200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"name":"CONACYT"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Emerg. Topics Comput."],"published-print":{"date-parts":[[2020,4,1]]},"DOI":"10.1109\/tetc.2017.2757937","type":"journal-article","created":{"date-parts":[[2017,9,29]],"date-time":"2017-09-29T18:43:07Z","timestamp":1506710587000},"page":"453-463","source":"Crossref","is-referenced-by-count":9,"title":["A Holistic Formulation for System Margining and Jitter Tolerance Optimization in Industrial Post-Silicon Validation"],"prefix":"10.1109","volume":"8","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-9633-2533","authenticated-orcid":false,"given":"Francisco Elias","family":"Rangel-Patino","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1175-249X","authenticated-orcid":false,"given":"Andres","family":"Viveros-Wacher","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2611-5618","authenticated-orcid":false,"given":"Jose Ernesto","family":"Rayas-Sanchez","sequence":"additional","affiliation":[]},{"given":"Ismael","family":"Duron-Rosales","sequence":"additional","affiliation":[]},{"given":"Edgar Andrei","family":"Vega-Ochoa","sequence":"additional","affiliation":[]},{"given":"Nagib","family":"Hakim","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6427-819X","authenticated-orcid":false,"given":"Enrique","family":"Lopez-Miralrio","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1080\/00401706.1993.10485320"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1002\/9780470770801"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1016\/0041-5553(67)90144-9"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-20859-1"},{"key":"ref31","article-title":"Aspects of the Matlab toolbox DACE","author":"lophaven","year":"2002","journal-title":"Informatics and Mathematical Modelling Technical Univ Denmark"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1214\/ss\/1177012413"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4757-3799-8"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1115\/1.2429697"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1023\/A:1008306431147"},{"key":"ref34","first-page":"72","article-title":"Computational investigation of low-discrepancy sequences in simulation algorithms for Bayesian networks","author":"cheng","year":"0","journal-title":"Proc 16th Conf Uncertainty Artif Intell"},{"key":"ref10","first-page":"360","article-title":"Accelerating jitter tolerance qualification for high speed serial interfaces","author":"fan","year":"0","journal-title":"Proc IEEE Int Symp Quality Electron Des"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/WSC.2009.5429320"},{"key":"ref11","doi-asserted-by":"crossref","first-page":"4","DOI":"10.1109\/MCAS.2004.1330746","article-title":"Equalization in high-speed communication systems","volume":"4","author":"liu","year":"2004","journal-title":"IEEE Circuits Syst Mag"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/LAMC.2016.7851268"},{"journal-title":"Comprehensive Functional Verification The Complete Industry Cycle","year":"2005","author":"wile","key":"ref13"},{"key":"ref14","first-page":"8","article-title":"Post-silicon is too late avoiding the ?50 million paperweight atarts with validated designs","author":"goodenough","year":"2010","journal-title":"Proc 47th ACM\/IEEE Des Autom Conf"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429502"},{"year":"2003","author":"tech","key":"ref16"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.931647"},{"journal-title":"Jitter Noise and Signal Integrity at High-Speed","year":"2007","author":"li","key":"ref18"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TADVP.2009.2012432"},{"journal-title":"Physical Layer Performance Testing the Bit Error Ratio (BER)","year":"2004","key":"ref28"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1049\/ree.1983.0030"},{"journal-title":"Total jitter measurement at low probability levels using optimized BERT scan method","year":"2005","key":"ref27"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISEMC.2011.6038414"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cds.2013.0159"},{"journal-title":"Total jitter measurement at low probability levels using optimized BERT scan method","year":"2005","key":"ref29"},{"journal-title":"High Speed Digital Design Design of High Speed Interconnects and Signaling","year":"2015","author":"zhang","key":"ref5"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCPMT.2011.2157916"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ICASID.2015.7405658"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837278"},{"key":"ref9","first-page":"1","article-title":"SMV methodology enhancements for high speed IO links of SoCs","author":"viveros-wacher","year":"2014","journal-title":"Proc IEEE VLSI Test Symp"},{"journal-title":"Intel platform and component validation - a commitment to quality reliability and compatibility","year":"2003","key":"ref1"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/ISEMC.2012.6351785"},{"key":"ref20","first-page":"17","article-title":"Bit-error rate estimation for bang-bang clock and data recovery circuit","author":"hong","year":"0","journal-title":"Proc 26th IEEE VLSI Test Symp"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/ISEMC.2013.6670430"},{"journal-title":"Peripheral Component Interconnect Express 3 1 Specification","year":"2016","key":"ref22"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/ISEMC.2011.6038418"},{"year":"2016","key":"ref21"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1080\/00401706.1989.10488474"},{"journal-title":"Serial Advanced Technology Attachment 3 2 Specification","year":"2016","key":"ref24"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.2113\/gsecongeo.58.8.1246"},{"journal-title":"Universal Serial Bus Revision 3 1 Specification","year":"2016","key":"ref23"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/EDAPS.2013.6724421"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2004.93"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1016\/j.paerosci.2005.02.001"},{"journal-title":"System-on-Chip Test Architectures Nanometer Design for Testability","year":"2008","author":"wang","key":"ref25"}],"container-title":["IEEE Transactions on Emerging Topics in Computing"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6245516\/9109372\/08053840.pdf?arnumber=8053840","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:29:35Z","timestamp":1642004975000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8053840\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,4,1]]},"references-count":47,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tetc.2017.2757937","relation":{},"ISSN":["2168-6750","2376-4562"],"issn-type":[{"type":"electronic","value":"2168-6750"},{"type":"electronic","value":"2376-4562"}],"subject":[],"published":{"date-parts":[[2020,4,1]]}}}