{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,1]],"date-time":"2026-05-01T22:40:46Z","timestamp":1777675246303,"version":"3.51.4"},"reference-count":39,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2022,7,1]],"date-time":"2022-07-01T00:00:00Z","timestamp":1656633600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2022,7,1]],"date-time":"2022-07-01T00:00:00Z","timestamp":1656633600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,7,1]],"date-time":"2022-07-01T00:00:00Z","timestamp":1656633600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"Center of Pervasive Communications and Computing"},{"DOI":"10.13039\/100005595","name":"University of California","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100005595","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Emerg. Topics Comput."],"published-print":{"date-parts":[[2022,7,1]]},"DOI":"10.1109\/tetc.2021.3115495","type":"journal-article","created":{"date-parts":[[2021,10,2]],"date-time":"2021-10-02T02:15:34Z","timestamp":1633140934000},"page":"1657-1664","source":"Crossref","is-referenced-by-count":11,"title":["Near Volatile and Non-Volatile Memory Processing in 3D Systems"],"prefix":"10.1109","volume":"10","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-4250-2290","authenticated-orcid":false,"given":"Maryam S.","family":"Hosseini","sequence":"first","affiliation":[{"name":"Department of Electrical Engineering and Computer Science, University of California, Irvine, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7877-6712","authenticated-orcid":false,"given":"Masoumeh","family":"Ebrahimi","sequence":"additional","affiliation":[{"name":"Department of Electronics and Embedded Systems, KTH Royal Institute of Technology, Stockholm, Sweden"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0352-0197","authenticated-orcid":false,"given":"Pooria","family":"Yaghini","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering and Computer Science, University of California, Irvine, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7216-0546","authenticated-orcid":false,"given":"Nader","family":"Bagherzadeh","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering and Computer Science, University of California, Irvine, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/216585.216588"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/3DIC.2009.5306577"},{"key":"ref3","article-title":"Hybrid memory cube consortium, HMC Specification 2.0","year":"2014"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2012.6242474"},{"key":"ref5","volume-title":"JESD235B: High Bandwidth Memory (HBM) DRAM Standard","year":"2018"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2015.7116279"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.24"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2013.6557176"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2012.2190369"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1016\/j.sse.2016.07.006"},{"key":"ref11","article-title":"Opportunities and challenges of emerging memory technologies","author":"Mutlu","year":"2017"},{"key":"ref12","article-title":"Reliability enhancement of many-core processors","author":"SeyyedHosseini","year":"2017"},{"key":"ref13","article-title":"Resilient 3D network-on-chip design and analysis","author":"Yaghini","year":"2016"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/2.375174"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/331532.331589"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1999.808425"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.1994.108"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/40.592312"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2014.55"},{"key":"ref20","article-title":"Mapping irregular applications to DIVA, a PIM-based data-intensive architecture","author":"Srivastava","year":"1999","journal-title":"Proc. ACM\/IEEE Conf. Supercomputing"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/2832911"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.136"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/2600212.2600213"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2014.6844483"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2015.22"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306797"},{"key":"ref27","first-page":"72","article-title":"The PARSEC benchmark suite: Characterization and architectural implications","volume-title":"Proc. Int. Conf. Parallel Architectures Compilation Techn.","author":"Bienia"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/1498765.1498785"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/225830.223990"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA45697.2020.00070"},{"key":"ref33","article-title":"Gem5-nvmain-hybrid-simulator","year":"2016"},{"key":"ref34","article-title":"Ramulator for processing in memory."},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/2508148.2485963"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2015.2414456"},{"key":"ref37","article-title":"DDR4 SDRAM, 16GB,"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/3131848"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2009.30"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2016.2546199"},{"key":"ref41","article-title":"DRAMPower: Open-source DRAM power & energy estimation tool","author":"Chandrasekar"}],"container-title":["IEEE Transactions on Emerging Topics in Computing"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6245516\/9874959\/09556138.pdf?arnumber=9556138","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,11]],"date-time":"2024-01-11T23:19:48Z","timestamp":1705015188000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9556138\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,7,1]]},"references-count":39,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tetc.2021.3115495","relation":{},"ISSN":["2168-6750","2376-4562"],"issn-type":[{"value":"2168-6750","type":"electronic"},{"value":"2376-4562","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,7,1]]}}}