{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,8]],"date-time":"2026-05-08T18:19:15Z","timestamp":1778264355047,"version":"3.51.4"},"reference-count":55,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2017,11,1]],"date-time":"2017-11-01T00:00:00Z","timestamp":1509494400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2017,11,1]],"date-time":"2017-11-01T00:00:00Z","timestamp":1509494400000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2017,11,1]],"date-time":"2017-11-01T00:00:00Z","timestamp":1509494400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2017,11,1]],"date-time":"2017-11-01T00:00:00Z","timestamp":1509494400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000183","name":"Army Research Office","doi-asserted-by":"publisher","award":["65513-CS"],"award-info":[{"award-number":["65513-CS"]}],"id":[{"id":"10.13039\/100000183","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"National Science Foundation, Division of Computer and Network Systems","doi-asserted-by":"publisher","award":["1652842"],"award-info":[{"award-number":["1652842"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100006732","name":"New York University\/New York University Abu Dhabi Center for Cyber Security","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100006732","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans.Inform.Forensic Secur."],"published-print":{"date-parts":[[2017,11]]},"DOI":"10.1109\/tifs.2017.2710954","type":"journal-article","created":{"date-parts":[[2017,6,1]],"date-time":"2017-06-01T18:06:38Z","timestamp":1496340398000},"page":"2668-2682","source":"Crossref","is-referenced-by-count":32,"title":["Testing the Trustworthiness of IC Testing: An Oracle-Less Attack on IC Camouflaging"],"prefix":"10.1109","volume":"12","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-9475-2796","authenticated-orcid":false,"given":"Muhammad","family":"Yasin","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ozgur","family":"Sinanoglu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jeyavijayan","family":"Rajendran","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2008.4700677"},{"key":"ref38","year":"2016","journal-title":"OpenSPARC T1 processor"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1984.5009364"},{"key":"ref32","author":"schobert","year":"2016","journal-title":"About Degate"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2602554"},{"key":"ref30","first-page":"197","article-title":"Stealthy dopant-level hardware trojans","author":"becker","year":"2013","journal-title":"Cryptographic Hardware and Embedded Systems"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/54.785838"},{"key":"ref36","first-page":"249","year":"2005","journal-title":"Synopsys User Manual TetraMAX ATPG User Guide Version X-2005 09"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/IDT.2015.7396725"},{"key":"ref34","first-page":"22","article-title":"Why is ATPG easy?","author":"prasad","year":"1999","journal-title":"Proc ACM\/IEEE Design Autom Conf"},{"key":"ref28","year":"2016","journal-title":"Reverse Engineering Software"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2014.2335155"},{"key":"ref29","first-page":"109","article-title":"Diffusion programmable device: The device to prevent reverse engineering","author":"shiozaki","year":"2014","journal-title":"IACR Cryptology ePrint Archive"},{"key":"ref2","author":"scheffer","year":"2016","journal-title":"EDA for IC System Design Verification and Testing"},{"key":"ref1","author":"wang","year":"2006","journal-title":"VLSI Test Principles and Architectures Design for Testability"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4419-9976-4_4"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/43.703941"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2006.105"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2008.4700647"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/378239.378388"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024805"},{"key":"ref25","year":"2015","journal-title":"Innovation is at Risk Losses of up to $4 Billion Annually due to IP Infringement"},{"key":"ref50","first-page":"339","article-title":"Scan based side channel attack on dedicated hardware implementations of data encryption standard","author":"yang","year":"2004","journal-title":"Proc IEEE Int Test Conf"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2398423"},{"key":"ref55","first-page":"139","article-title":"Activation of logic encrypted chips: Pre-test or post-test?","author":"yasin","year":"2016","journal-title":"Proc Design Autom Test Eur"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2016.7495588"},{"key":"ref53","first-page":"495","article-title":"Securing computer hardware using 3D integrated circuit (IC) technology and split manufacturing for obfuscation","author":"imeson","year":"2013","journal-title":"Proc Usenix Security Conf"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1145\/2948618.2948619"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2511144"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2010.284"},{"key":"ref40","article-title":"Atalanta: An efficient ATPG for combinational circuits","author":"lee","year":"1993"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/2508859.2516656"},{"key":"ref13","author":"berry","year":"2014","journal-title":"Outsourcing Test—What are the Most Valuable Engagement Periods?"},{"key":"ref14","year":"2014","journal-title":"Silicon Laboratories and ASE Announce Milestone Shipment of 10 Million Tested Integrated Circuits"},{"key":"ref15","year":"2005","journal-title":"Testbed Overview"},{"key":"ref16","year":"2005","journal-title":"Test Services Overview"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/2966986.2967012"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.14722\/ndss.2015.23218"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.3850\/9783981537079_0915"},{"key":"ref4","volume":"17","author":"bushnell","year":"2000","journal-title":"Essentials of Electronic Testing for Digital Memory and Mixed-Signal VLSI Circuits"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/54.7962"},{"key":"ref6","article-title":"Camouflaging a standard cell based integrated circuit","author":"chow","year":"2012"},{"key":"ref5","year":"2015","journal-title":"Syphermedia Library Circuit Camouflage Technology"},{"key":"ref8","year":"2012","journal-title":"Intel's 22-nm Tri-gate Transistors Exposed"},{"key":"ref7","year":"0","journal-title":"Texas Instruments 4377401 Baseband Processor TSMC 65 nm Process Transistor Characterization"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.862745"},{"key":"ref9","first-page":"291","article-title":"Active hardware metering for intellectual property protection and security","author":"alkabani","year":"2007","journal-title":"Proc USENIX Security07"},{"key":"ref46","year":"2014","journal-title":"Iran Claims to Have Reverse-Engineered US Spy Drone"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/ISMVL.2010.35"},{"key":"ref48","author":"bushnell","year":"2000","journal-title":"Essentials of Electronic Testing for Digital Memory and Mixed-Signal VLSI Circuits"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/2.769444"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1145\/2660267.2660301"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1145\/2966986.2967065"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-19249-9_21"},{"key":"ref43","first-page":"837","article-title":"Robust techniques for watermarking sequential circuit designs","author":"oliveira","year":"1999","journal-title":"Proc IEEE\/ACM Design Autom Conf"}],"container-title":["IEEE Transactions on Information Forensics and Security"],"original-title":[],"link":[{"URL":"http:\/\/ieeexplore.ieee.org\/ielaam\/10206\/7990663\/7937844-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10206\/7990663\/07937844.pdf?arnumber=7937844","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,8]],"date-time":"2022-04-08T18:51:55Z","timestamp":1649443915000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7937844\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,11]]},"references-count":55,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tifs.2017.2710954","relation":{},"ISSN":["1556-6013","1556-6021"],"issn-type":[{"value":"1556-6013","type":"print"},{"value":"1556-6021","type":"electronic"}],"subject":[],"published":{"date-parts":[[2017,11]]}}}