{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,27]],"date-time":"2026-03-27T02:44:40Z","timestamp":1774579480145,"version":"3.50.1"},"reference-count":60,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2019,4,1]],"date-time":"2019-04-01T00:00:00Z","timestamp":1554076800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,4,1]],"date-time":"2019-04-01T00:00:00Z","timestamp":1554076800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,4,1]],"date-time":"2019-04-01T00:00:00Z","timestamp":1554076800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"Singapore Ministry of Education Academic Research Fund (AcRF) Tier II","award":["MOE 2015-T2-2-013"],"award-info":[{"award-number":["MOE 2015-T2-2-013"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans.Inform.Forensic Secur."],"published-print":{"date-parts":[[2019,4]]},"DOI":"10.1109\/tifs.2018.2870835","type":"journal-article","created":{"date-parts":[[2018,9,17]],"date-time":"2018-09-17T18:29:36Z","timestamp":1537208976000},"page":"1109-1123","source":"Crossref","is-referenced-by-count":96,"title":["Reliable and Modeling Attack Resistant Authentication of Arbiter PUF in FPGA Implementation With Trinary Quadruple Response"],"prefix":"10.1109","volume":"14","author":[{"given":"Siarhei S.","family":"Zalivaka","sequence":"first","affiliation":[]},{"given":"Alexander A.","family":"Ivaniuk","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8897-6176","authenticated-orcid":false,"given":"Chip-Hong","family":"Chang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2004.1346548"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2014.2300635"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/CSAC.2002.1176287"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2013.6581558"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2014.6855565"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2015.0522"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/PERCOMW.2016.7457162"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062315"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/TIFS.2013.2279798"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/2815621"},{"key":"ref60","first-page":"427","article-title":"AES on FPGA from the fastest to the smallest","author":"good","year":"2005","journal-title":"Proc 9th Int Workshop Cryptograph Hardw Embed Syst (CHES)"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2015.7058919"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2017.8050671"},{"key":"ref29","doi-asserted-by":"crossref","first-page":"649","DOI":"10.1109\/TCAD.2013.2296525","article-title":"Statistical analysis of MUX-based physical unclonable functions","volume":"33","author":"lao","year":"2014","journal-title":"IEEE Trans Comput -Aided Design Integr Circuits Syst"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2014.6742840"},{"key":"ref1","year":"2015","journal-title":"FPGA Market Size Share Analysis Research Report 2020"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/WIFS.2010.5711471"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2015.7140233"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2010.25"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.3103\/S0146411615030049"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2016.7428066"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2017.7918334"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-14971-4_2"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2488493"},{"key":"ref51","first-page":"1104","article-title":"PUF-FSM: A controlled strong PUF","volume":"37","author":"gao","year":"2018","journal-title":"IEEE Trans Comput -Aided Design Integr Circuits Syst"},{"key":"ref59","first-page":"319","article-title":"Very compact FPGA implementation of the AES algorithm","author":"chodowiec","year":"2003","journal-title":"Proc 9th Int Workshop Cryptograph Hardw Embed Syst (CHES)"},{"key":"ref58","doi-asserted-by":"crossref","first-page":"27","DOI":"10.1007\/978-1-4419-8080-9_2","article-title":"Hardware implementation of hash functions","author":"shi","year":"2012","journal-title":"Introduction to Hardware Security and Trust"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.1109\/TDSC.2016.2536609"},{"key":"ref56","author":"zhang","year":"2018","journal-title":"CMOS Dynamic multi-key obfuscation structure for strong PUFs"},{"key":"ref55","article-title":"SP 800-22 Rev. 1a. A statistical test suite for random and pseudorandom number generators for cryptographic applications","author":"bassham","year":"2010"},{"key":"ref54","first-page":"1","article-title":"An efficient reliable PUF-based cryptographic key generator in 65 nm CMOS","author":"bhargava","year":"2014","journal-title":"Proc Design and Test in Eur (DATE) Conf"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/ReConFig.2010.24"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/AsianHOST.2016.7835567"},{"key":"ref10","author":"tuyls","year":"2007","journal-title":"Security with Noisy Data On Private Biometrics Secure Key Storage and Anti-Counterfeiting"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-74735-2_5"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2008.4542137"},{"key":"ref12","first-page":"390","article-title":"Uniqueness enhancement of PUF responses based on the locations of random outputting RS latches","author":"yamamoto","year":"2011","journal-title":"Proc 9th Int Workshop Cryptograph Hardw Embed Syst (CHES)"},{"key":"ref13","first-page":"382","article-title":"An analysis of delay based PUF implementations on FPGA","author":"morozov","year":"2010","journal-title":"Proc Int Symp Appl Reconfigurable Comput (ARC'07)"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2014.6927449"},{"key":"ref15","first-page":"9","article-title":"Physical unclonable functions for device authentication and secret key generation","author":"suh","year":"2007","journal-title":"Proc Design Automat Conf (DAC)"},{"key":"ref16","author":"prophet","year":"2016","journal-title":"Xilinx to Add PUF Security to Zynq Devices"},{"key":"ref17","year":"2015","journal-title":"Altera Reveals Stratix 10 With Intrinsic-ID&#x2019;s PUF Technology"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2016.7495550"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1007\/s11390-016-1616-8"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI.Design.2010.54"},{"key":"ref3","article-title":"Anti-tamper microchip package based on thermal nanofluids or fluids","author":"das","year":"2012"},{"key":"ref6","author":"peterson","year":"2013","journal-title":"Developing tamper resistant designs with Xilinx Virtex-6 and 7 series FPGAs"},{"key":"ref5","first-page":"357","article-title":"Periodic licensing of FPGA based intellectual property","author":"couture","year":"2006","journal-title":"Proc IEEE Int Conf Field Program Technol (ICFPT)"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2282282"},{"key":"ref7","first-page":"118","article-title":"A chaotic IP watermarking in physical layout level based on FPGA","volume":"20","author":"liang","year":"2011","journal-title":"Radioengineering"},{"key":"ref49","author":"delvaux","year":"2017","journal-title":"Machine Learning Attacks on PolyPUF OBPUF RPUF and PUF&#x2013;FSM"},{"key":"ref9","first-page":"103","article-title":"Hardware metering: A survey","author":"koushanfar","year":"2011","journal-title":"Introduction to Hardware Security and Trust"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2427259"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4419-5906-5"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-77026-8_30"},{"key":"ref47","author":"mahmoud","year":"2013","journal-title":"Combined Modeling and Side Channel Attacks on Strong PUFs"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2008.4700636"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/4.287"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/54.211530"},{"key":"ref43","first-page":"237","article-title":"Modeling attacks on physical unclonable functions","author":"r\u00fchrmair","year":"2010","journal-title":"Proc ACM Conf Comput Commun Secur (CCS)"}],"container-title":["IEEE Transactions on Information Forensics and Security"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10206\/8517164\/08466897.pdf?arnumber=8466897","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,13]],"date-time":"2022-07-13T21:09:48Z","timestamp":1657746588000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8466897\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,4]]},"references-count":60,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tifs.2018.2870835","relation":{},"ISSN":["1556-6013","1556-6021"],"issn-type":[{"value":"1556-6013","type":"print"},{"value":"1556-6021","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019,4]]}}}