{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,24]],"date-time":"2026-07-24T18:46:15Z","timestamp":1784918775238,"version":"3.55.0"},"reference-count":47,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2020,1,1]],"date-time":"2020-01-01T00:00:00Z","timestamp":1577836800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,1,1]],"date-time":"2020-01-01T00:00:00Z","timestamp":1577836800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,1,1]],"date-time":"2020-01-01T00:00:00Z","timestamp":1577836800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans.Inform.Forensic Secur."],"published-print":{"date-parts":[[2020]]},"DOI":"10.1109\/tifs.2020.2977534","type":"journal-article","created":{"date-parts":[[2020,3,2]],"date-time":"2020-03-02T20:43:58Z","timestamp":1583181838000},"page":"2808-2823","source":"Crossref","is-referenced-by-count":16,"title":["Resilient System-on-Chip Designs With NoC Fabrics"],"prefix":"10.1109","volume":"15","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-0050-8379","authenticated-orcid":false,"given":"Atul Prasad","family":"Deb Nath","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Srivalli","family":"Boddupalli","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6082-6961","authenticated-orcid":false,"given":"Swarup","family":"Bhunia","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Sandip","family":"Ray","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2008.69"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2007.32"},{"key":"ref33","first-page":"1","article-title":"Real-time trust evaluation in integrated circuits","author":"jin","year":"2014","journal-title":"Proc Design Autom Test Eur Conf Exhibition (DATE)"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2011.5954999"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2018.00081"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2013.6691167"},{"key":"ref37","doi-asserted-by":"crossref","DOI":"10.1016\/j.procs.2017.05.139","article-title":"Towards protected MPSoC communication for information protection against a malicious NoC","author":"sep\u00falveda","year":"2017","journal-title":"Proc Int Conf Comput Sci (ICCS)"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2016.25"},{"key":"ref35","first-page":"1136","article-title":"Packet Security with Path Sensitization for NoCs","author":"travis boraten","year":"2016","journal-title":"Design Automation Test in Europe Conference Exhibition (DATE)"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593144"},{"key":"ref10","year":"2019","journal-title":"Intel Baytrail Products"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/INA-OCMC.2015.9"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2015.7372616"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TIFS.2017.2658544"},{"key":"ref13","author":"shuler","year":"2013","journal-title":"Majority of Leading China Semiconductor Companies Rely on Arteris Network-on-Chip Interconnect IP"},{"key":"ref14","article-title":"SoC reliability features in the FlexNoC resilience package: A complementary IP packagefor use with arteris FlexNoC IP","author":"probell","year":"2014"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2018.8297409"},{"key":"ref16","author":"shuler","year":"2018","journal-title":"How SoC Interconnect Enables Flexible Architecture for ADAS and Autonomous Car Designs"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2012.6339273"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2017.2691348"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2007.54"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/IVSW.2018.8494856"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2017.2714641"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/NAECON.2018.8556746"},{"key":"ref3","year":"2015","journal-title":"Intel Xeon Processor E7-8800\/4800\/2800 Product Families Specification Update"},{"key":"ref6","first-page":"1","article-title":"On-chip networks","volume":"12","author":"jerger","year":"2017","journal-title":"Synth Lect Comput Arch"},{"key":"ref29","first-page":"396","article-title":"MERO: A statistical approach for hardware trojan detection","author":"chakraborty","year":"2009","journal-title":"Proc Workshop Cryptographic Hardware Embedded Syst"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.4378780"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744823"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2508859.2516654"},{"key":"ref2","year":"2012","journal-title":"X86&#x2013;64 Data16 Prefix on Direct Jumps Allows Sandbox Escape on AMD Cpus Nativeclient Bug Tracker"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/HLDVT.2009.5340158"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/2775054.2694366"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2018.00070"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2009.4919636"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2017.03.002"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/2906147"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744912"},{"key":"ref21","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/2024716.2024718","article-title":"The Gem5 simulator","volume":"39","author":"binkert","year":"2011","journal-title":"ACM SIGARCH Comput Archit News"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1145\/2508148.2485972"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2014.44"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS.2015.37"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/2638555"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2012.24"},{"key":"ref26","doi-asserted-by":"crossref","DOI":"10.1016\/j.vlsi.2019.12.007","article-title":"Defense-in-depth: A recipe for logic locking to prevail","author":"rahman","year":"2020","journal-title":"Integration"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2016.12.010"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/NAECON.2017.8268803"}],"container-title":["IEEE Transactions on Information Forensics and Security"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10206\/8833568\/09019608.pdf?arnumber=9019608","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T17:00:15Z","timestamp":1651078815000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9019608\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020]]},"references-count":47,"URL":"https:\/\/doi.org\/10.1109\/tifs.2020.2977534","relation":{},"ISSN":["1556-6013","1556-6021"],"issn-type":[{"value":"1556-6013","type":"print"},{"value":"1556-6021","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020]]}}}