{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,4,19]],"date-time":"2024-04-19T10:08:45Z","timestamp":1713521325751},"reference-count":35,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2015,8,1]],"date-time":"2015-08-01T00:00:00Z","timestamp":1438387200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Ind. Inf."],"published-print":{"date-parts":[[2015,8]]},"DOI":"10.1109\/tii.2015.2435696","type":"journal-article","created":{"date-parts":[[2015,5,21]],"date-time":"2015-05-21T19:01:28Z","timestamp":1432234888000},"page":"897-906","source":"Crossref","is-referenced-by-count":9,"title":["Handling Exceptions in Petri Net-Based Digital Architecture: From Formalism to Implementation on FPGAs"],"prefix":"10.1109","volume":"11","author":[{"given":"Helene","family":"Leroux","sequence":"first","affiliation":[]},{"given":"David","family":"Andreu","sequence":"additional","affiliation":[]},{"given":"Karen","family":"Godary-Dejean","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref33","year":"0"},{"key":"ref32","year":"0","journal-title":"Time petri Net Analyzer"},{"key":"ref31","article-title":"Integrating implementation properties in analysis of Petri nets handling exceptions","author":"leroux","year":"0","journal-title":"Proc 12th IFAC-IEEE Int Workshop Discrete Event Syst"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-73094-1_7"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/TSMC.2013.2258907"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2014.44"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TII.2011.2123908"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/HSI.2014.6860484"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1007\/s00170-008-1497-2"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TIE.2009.2038946"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.2478\/eletel-2013-0040"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/IECON.2013.6699475"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.2478\/v10177-012-0055-x"},{"key":"ref17","first-page":"149","article-title":"Digital systems synthesis based on direct translation of Petri net model","author":"sudacevschi","year":"0","journal-title":"Proc 11th Int Conf Dev Appl Syst"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2008.54"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/EWDTS.2008.5580151"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-75596-8_37"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TII.2005.844433"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/SBCCI.2002.1137663"},{"key":"ref3","first-page":"1","article-title":"Modeling, analysis and control of discrete event systems as Petri nets","author":"silva","year":"2014","journal-title":"Encyclopedia of Systems and Control"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-54900-7_56"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1007\/s10626-013-0159-1"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1016\/j.arcontrol.2013.09.001"},{"key":"ref8","article-title":"Petri nets based methodology for communicating neuroprosthesis design and prototyping","author":"souquet","year":"0","journal-title":"Proc Int Symp Appl Sci Biomed Commun Technol (ISABEL’08)"},{"key":"ref7","author":"baier","year":"2008","journal-title":"Principles of Model Checking"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-41010-9_7"},{"key":"ref9","author":"yakovlev","year":"2013","journal-title":"Hardware Design And Petri Nets"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1088\/1741-2560\/6\/2\/026001"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.2478\/v10177-012-0006-6"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.2478\/v10177-010-0002-7"},{"key":"ref21","first-page":"1","article-title":"Distributed control systems design as Petri nets for FPGAs","volume":"4","author":"bukowiec","year":"2013","journal-title":"Int J Design Anal Tools Integr Circuits Syst"},{"key":"ref24","article-title":"A sequential control language for industrial automation","author":"theorin","year":"2014"},{"key":"ref23","article-title":"Computing synccharts reactions","author":"andr\u00e9","year":"2003"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ICSMC.1995.538189"},{"key":"ref25","first-page":"328","article-title":"Coupling asynchrony and interrupts: Place chart nets","volume":"1248","author":"kishinevsky","year":"0","journal-title":"Proc Int Conf Agric Technol Plant Nutr (ICATPN)"}],"container-title":["IEEE Transactions on Industrial Informatics"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9424\/7169637\/07111285.pdf?arnumber=7111285","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:46:19Z","timestamp":1642005979000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7111285\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,8]]},"references-count":35,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tii.2015.2435696","relation":{},"ISSN":["1551-3203","1941-0050"],"issn-type":[{"value":"1551-3203","type":"print"},{"value":"1941-0050","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,8]]}}}