{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,1]],"date-time":"2026-06-01T23:29:32Z","timestamp":1780356572457,"version":"3.54.1"},"reference-count":26,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2022,1,1]],"date-time":"2022-01-01T00:00:00Z","timestamp":1640995200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2022,1,1]],"date-time":"2022-01-01T00:00:00Z","timestamp":1640995200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,1,1]],"date-time":"2022-01-01T00:00:00Z","timestamp":1640995200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Instrum. Meas."],"published-print":{"date-parts":[[2022]]},"DOI":"10.1109\/tim.2022.3180418","type":"journal-article","created":{"date-parts":[[2022,6,6]],"date-time":"2022-06-06T20:04:05Z","timestamp":1654545845000},"page":"1-9","source":"Crossref","is-referenced-by-count":2,"title":["Time-Sliced Architecture for Efficient Accelerator to Detrend High-Definition Electroencephalograms"],"prefix":"10.1109","volume":"71","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-9871-800X","authenticated-orcid":false,"given":"Rakshit","family":"Mittal","sequence":"first","affiliation":[{"name":"Department of INFRES, Telecom Paris, LTCI Laboratory, Institut Polytechnique de Paris, Palaiseau, France"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4471-9979","authenticated-orcid":false,"given":"A. Amalin","family":"Prince","sequence":"additional","affiliation":[{"name":"Department of Electrical and Electronics Engineering, Birla Institute of Technology &#x0026; Science, Pilani, Sancoale, Goa, India"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5759-6632","authenticated-orcid":false,"given":"Agastinose Ronickom Jac","family":"Fredo","sequence":"additional","affiliation":[{"name":"School of Biomedical Engineering, Indian Institute of Technology (BHU), Varanasi, Uttar Pradesh, India"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TIM.2020.3047488"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TIM.2021.3137159"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TIM.2021.3121473"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TIM.2021.3069026"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/RBME.2020.2969915"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1016\/j.compbiomed.2021.104434"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1016\/j.bspc.2021.102741"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TIM.2017.2775358"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/IECON.2016.7793218"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1016\/j.sigpro.2011.08.005"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.2196\/16194"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TBCAS.2018.2876240"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TIM.2020.2984142"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1016\/j.bspc.2015.06.001"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1016\/j.bspc.2021.102927"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TIM.2020.3018235"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ReCoSoC.2015.7238091"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1016\/j.measurement.2019.03.028"},{"key":"ref19","article-title":"Comparative evaluation of state-of-the-art algorithms for SSVEP-based BCIs","author":"Oikonomou","year":"2016","journal-title":"arXiv:1602.00904"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-28365-9_2"},{"key":"ref21","doi-asserted-by":"crossref","first-page":"39","DOI":"10.1016\/B978-0-12-415993-8.00002-5","article-title":"Background","volume-title":"Structured Parallel Programming","author":"McCool","year":"2012"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1155\/2018\/9861350"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1016\/j.cmpb.2018.02.009"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ICCONS.2018.8662998"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ICCSP.2016.7754244"},{"key":"ref26","first-page":"1","article-title":"Hardware-efficient EVD processor architecture in FastICA for epileptic seizure detection","volume-title":"Proc. Asia Pacific Signal Inf. Process. Assoc. Annu. Summit Conf.","author":"Shih"}],"container-title":["IEEE Transactions on Instrumentation and Measurement"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/19\/9717300\/09789133.pdf?arnumber=9789133","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,2,1]],"date-time":"2024-02-01T02:48:48Z","timestamp":1706755728000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9789133\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022]]},"references-count":26,"URL":"https:\/\/doi.org\/10.1109\/tim.2022.3180418","relation":{},"ISSN":["0018-9456","1557-9662"],"issn-type":[{"value":"0018-9456","type":"print"},{"value":"1557-9662","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022]]}}}