{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T22:17:39Z","timestamp":1740176259739,"version":"3.37.3"},"reference-count":43,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2015,7,1]],"date-time":"2015-07-01T00:00:00Z","timestamp":1435708800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100002551","name":"Seoul National University","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100002551","id-type":"DOI","asserted-by":"publisher"}]},{"name":"IT R&D program"},{"name":"MKE"},{"DOI":"10.13039\/501100003662","name":"KEIT","doi-asserted-by":"publisher","award":["10041608"],"award-info":[{"award-number":["10041608"]}],"id":[{"id":"10.13039\/501100003662","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Embedded System Software"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Multi-Scale Comp. Syst."],"published-print":{"date-parts":[[2015,7,1]]},"DOI":"10.1109\/tmscs.2015.2498549","type":"journal-article","created":{"date-parts":[[2015,11,6]],"date-time":"2015-11-06T15:12:25Z","timestamp":1446822745000},"page":"138-149","source":"Crossref","is-referenced-by-count":4,"title":["Hybrid Main Memory for High Bandwidth Multi-Core System"],"prefix":"10.1109","volume":"1","author":[{"given":"Dongki","family":"Kim","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sungjoo","family":"Yoo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sunggu","family":"Lee","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2007.377981"},{"article-title":"USIMM: The Utah simulated memory module","year":"2012","author":"chatterjee","key":"ref38"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/2656045.2656049"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2011.5749752"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.46"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815980"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2013.6557148"},{"key":"ref36","first-page":"63","article-title":"Parallelism-aware batch scheduling: Enhancing both performance and fairness of shared DRAM systems","author":"mutlu","year":"0","journal-title":"Proc 35th Annu Int Symp Comput Archit"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS.2011.40"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/1450058.1450064"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228519"},{"year":"2001","key":"ref40"},{"article-title":"BATMAN: Maximizing bandwidth utilization of hybrid memory systems","year":"2015","author":"chou","key":"ref11"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.56"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2012.6378661"},{"key":"ref14","first-page":"404","article-title":"Die-stacked DRAM caches for servers hit ratio, latency, or bandwidth? have it all with footprint cache","author":"jevdjic","year":"0","journal-title":"Proc 40th Annu Int Symp Comput Archit"},{"key":"ref15","first-page":"93","article-title":"Exploring hybrid memory for GPU energy efficiency through software-hardware co-design","author":"wang","year":"0","journal-title":"Proc Int Conf Parallel Archit Compilation Tech"},{"article-title":"Memory channel that supports near memory and far memory access","year":"0","author":"nale","key":"ref16"},{"article-title":"Apparatus and method for implementing a multi- level memory hierarchy having different operating modes","year":"2013","author":"ramanujan","key":"ref17"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2007.4601880"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056059"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024939"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2012.6169027"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2010.5416645"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2350073"},{"key":"ref6","first-page":"282","article-title":"Accelerating write by exploiting PCM asymmetries","author":"yue","year":"0","journal-title":"Proc IEEE 19th Int Symp High Perform Comput Archit"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593217"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.10"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555760"},{"key":"ref7","article-title":"Partial-SET: Write speedup of PCM main memory","author":"li","year":"0","journal-title":"Proc Des Autom Test Eur Conf"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1147\/rd.524.0465"},{"key":"ref1","article-title":"Co-architecting controllers and DRAM to enhance DRAM process scaling","author":"kang","year":"0","journal-title":"Proc Memory Forum A Workshop 41st Int Symp Comput Archit"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763155"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.30"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.51"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155673"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1145\/511334.511343"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/RSP.2014.6966901"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250713"},{"key":"ref23","first-page":"500","article-title":"A 58\ufffdnm 1.8V 1 Gb PRAM with 6.4 MB\/s program BW","author":"chung","year":"0","journal-title":"Proc Int Solid-State Circuits Conf"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1816014"},{"key":"ref43","first-page":"270","article-title":"Flow and stretch metrics for scheduling continuous job streams","author":"bender","year":"0","journal-title":"9th Ann ACM-SIAM Symp on Discrete Algorithms"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669117"}],"container-title":["IEEE Transactions on Multi-Scale Computing Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6687315\/7358202\/07321800.pdf?arnumber=7321800","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:47:24Z","timestamp":1641988044000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7321800\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,7,1]]},"references-count":43,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tmscs.2015.2498549","relation":{},"ISSN":["2332-7766"],"issn-type":[{"type":"electronic","value":"2332-7766"}],"subject":[],"published":{"date-parts":[[2015,7,1]]}}}