{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,31]],"date-time":"2025-10-31T07:44:23Z","timestamp":1761896663195,"version":"3.37.3"},"reference-count":52,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2018,4,1]],"date-time":"2018-04-01T00:00:00Z","timestamp":1522540800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"name":"INTEL11EG01"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Multi-Scale Comp. Syst."],"published-print":{"date-parts":[[2018,4,1]]},"DOI":"10.1109\/tmscs.2017.2768362","type":"journal-article","created":{"date-parts":[[2017,11,2]],"date-time":"2017-11-02T20:50:06Z","timestamp":1509655806000},"page":"113-126","source":"Crossref","is-referenced-by-count":7,"title":["A Systematic and Realistic Network-on-Chip Traffic Modeling and Generation Technique for Emerging Many-Core Systems"],"prefix":"10.1109","volume":"4","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-9348-4662","authenticated-orcid":false,"given":"Weichen","family":"Liu","sequence":"first","affiliation":[]},{"given":"Zhe","family":"Wang","sequence":"additional","affiliation":[]},{"given":"Peng","family":"Yang","sequence":"additional","affiliation":[]},{"given":"Jiang","family":"Xu","sequence":"additional","affiliation":[]},{"given":"Bin","family":"Li","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5383-9561","authenticated-orcid":false,"given":"Ravi","family":"Lyer","sequence":"additional","affiliation":[]},{"given":"Ramesh","family":"Illikkal","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2010.204"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2006.4380859"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1995.524546"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2007.18"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/MNRC.2008.4683371"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2006.4380845"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1145\/1999946.1999971"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2000.842273"},{"year":"2013","key":"ref35"},{"article-title":"Benchmarking modern multiprocessors","year":"2011","author":"bienia","key":"ref34"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/1629435.1629498"},{"key":"ref27","first-page":"266","article-title":"Quantum-like effects in network-on-chip buffers behavior","author":"bogdan","year":"2007","journal-title":"Proc 44th ACM\/IEEE Des Autom Conf"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ICICT.2007.375388"},{"key":"ref2","first-page":"1508","article-title":"H. 264 HDTV decoder using application-specific\n networks-on-chip","author":"xu","year":"2005","journal-title":"Proc IEEE Int Conf Multimedia Expo"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379048"},{"key":"ref20","article-title":"A generic traffic model for on-chip interconnection networks","author":"bahn","year":"2008","journal-title":"Proc Int Workshop Netw Chip Architect"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2010.35"},{"key":"ref21","first-page":"184","article-title":"Traffic generation and performance evaluation for mesh-based nocs","author":"tedesco","year":"2005","journal-title":"Proc Annu Symp Integr Circuits Syst Design"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2014.7008760"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/HPCS.2010.5547064"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/2678373.2665691"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2009.4919653"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1145\/1629435.1629445"},{"year":"1991","key":"ref51","article-title":"Handbook of Genetic Algorithms"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS.2008.49"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.2010691"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1561\/1000000011"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/92.863627"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/HPCC-CSS-ICESS.2015.60"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2016.7428097"},{"key":"ref14","first-page":"770","article-title":"A case study in networks-on-chip design for embedded video","author":"xu","year":"2004","journal-title":"Proc Des Autom Test Eur Conf Exhib"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/1921249.1921258"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2011.49"},{"article-title":"An initiative towards open network-on-chip benchmarks","year":"2007","author":"grecu","key":"ref17"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.820523"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/MASCOTS.2006.9"},{"year":"2005","key":"ref4","article-title":"Stmicroelectronics unveils innovative\n network-on-chip technology for new system-on-chip interconnect paradigm"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/1132952.1132953"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2111270"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2535359"},{"year":"2017","key":"ref8"},{"key":"ref7","article-title":"Realistic workload characterization and analysis for networks-on-chip design","author":"gratz","year":"2010","journal-title":"Proceedings of the Workshop on Chip Multiprocessor Memory Systems and Interconnect"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1016\/j.future.2016.09.012"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2004.65"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1145\/2950051"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt:20070111"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2016.2643669"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062323"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1145\/966785.966788"},{"journal-title":"Load Balancing in Parallel Computers Theory and Practice","year":"1997","author":"xu","key":"ref41"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:20045092"},{"key":"ref43","first-page":"16","article-title":"Energy-aware communication and task scheduling for network-on-chip architectures under real-time\n constraints","author":"hu","year":"2004","journal-title":"Proc Des Autom Test Eur Conf Exhib"}],"container-title":["IEEE Transactions on Multi-Scale Computing Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6687315\/8387744\/08094019.pdf?arnumber=8094019","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:23:14Z","timestamp":1642004594000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8094019\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,4,1]]},"references-count":52,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tmscs.2017.2768362","relation":{},"ISSN":["2332-7766","2372-207X"],"issn-type":[{"type":"electronic","value":"2332-7766"},{"type":"electronic","value":"2372-207X"}],"subject":[],"published":{"date-parts":[[2018,4,1]]}}}