{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,17]],"date-time":"2025-03-17T04:07:05Z","timestamp":1742184425110,"version":"3.38.0"},"reference-count":34,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2002,11,1]],"date-time":"2002-11-01T00:00:00Z","timestamp":1036108800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Parallel Distrib. Syst."],"published-print":{"date-parts":[[2002,11]]},"DOI":"10.1109\/tpds.2002.1058096","type":"journal-article","created":{"date-parts":[[2003,1,3]],"date-time":"2003-01-03T17:55:00Z","timestamp":1041616500000},"page":"1124-1138","source":"Crossref","is-referenced-by-count":2,"title":["Optimal algorithms for the channel-assignment problem on a reconfigurable array of processors with wider bus networks"],"prefix":"10.1109","volume":"13","author":[{"family":"Shi-Jinn Horng","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Horng-Ren Tsai","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Yi Pan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.","family":"Seitzer","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1287\/opre.31.1.24"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1364\/AO.27.001742"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/C-M.1981.220290"},{"volume-title":"Algorithmic Graph Theory and Perfect Graphs","year":"1980","author":"Golumbic","key":"ref4"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1979.1675260"},{"volume-title":"Advanced Computer ArchitectureParallelism, Scalability, Programmability","year":"1993","author":"Hwang","key":"ref6"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/12.8729"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/71.382325"},{"key":"ref9","first-page":"138","article-title":"The Power of List Ranking on a Reconfigurable Array of Processors with Wider Bus Networks","volume":"28","author":"Kao","year":"1996","journal-title":"The Australian Computer J."},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MPPOI.1998.682145"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/83.784435"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/34.21792"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/71.706044"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/43.293945"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1016\/0743-7315(89)90022-1"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/12.277290"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1007\/BF01994843"},{"volume-title":"Physical Design Automation of VLSI Sysyem","year":"1988","author":"Preas","key":"ref18"},{"key":"ref19","first-page":"134","volume-title":"Basic VLSI Design","author":"Pucknell","year":"1994"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1006\/jpdc.1994.1086"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1983.1676213"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1142\/S0129626495000023"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-50728-0_52"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JCIT.1990.128289"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4684-5511-3_32"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1016\/0020-0190(92)90244-P"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1982.1585598"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1006\/jpdc.1997.1385"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TCS.1980.1084890"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/71.80177"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/12.55698"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1006\/jpdc.2000.1644"},{"key":"ref33","first-page":"162","article-title":"An Optimal Parallel Algorithm for Minimum Coloring of Intervals","volume-title":"Proc. Int\u2019l Conf. Parallel Processing","volume":"III","author":"Yu"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1016\/0020-0190(93)90267-D"}],"container-title":["IEEE Transactions on Parallel and Distributed Systems"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/71\/22803\/01058096.pdf?arnumber=1058096","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,16]],"date-time":"2025-03-16T04:58:09Z","timestamp":1742101089000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1058096\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2002,11]]},"references-count":34,"journal-issue":{"issue":"11","published-print":{"date-parts":[[2002,11]]}},"URL":"https:\/\/doi.org\/10.1109\/tpds.2002.1058096","relation":{},"ISSN":["1045-9219"],"issn-type":[{"type":"print","value":"1045-9219"}],"subject":[],"published":{"date-parts":[[2002,11]]}}}