{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,1]],"date-time":"2025-10-01T18:17:46Z","timestamp":1759342666334},"reference-count":29,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2015,2,1]],"date-time":"2015-02-01T00:00:00Z","timestamp":1422748800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Parallel Distrib. Syst."],"published-print":{"date-parts":[[2015,2]]},"DOI":"10.1109\/tpds.2014.2306411","type":"journal-article","created":{"date-parts":[[2014,3,13]],"date-time":"2014-03-13T18:02:42Z","timestamp":1394733762000},"page":"444-454","source":"Crossref","is-referenced-by-count":8,"title":["FPS: A Fair-Progress Process Scheduling Policy on Shared-Memory Multiprocessors"],"prefix":"10.1109","volume":"26","author":[{"given":"Chenggang","family":"Wu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jin","family":"Li","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Di","family":"Xu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pen-Chung","family":"Yew","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jianjun","family":"Li","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhenjiang","family":"Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.24"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/378993.379244"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/511334.511343"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.2003.1240622"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ICPADS.2006.59"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605403"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253197"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/859654.859657"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2001.953283"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2005.27"},{"key":"ref28","article-title":"A Step towards Transparent Integration if Input-Consciousness into Dynamic Program Optimizations","author":"tian","year":"2011","journal-title":"Proc ACM SIGPLAN Int Conf Object-Oriented Program Syst Lang Appl (OOPSLA)"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1854273.1854306"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/1869459.1869471"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2007.4336197"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.21"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155650"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.39"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1006209.1006246"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1254882.1254886"},{"key":"ref2","article-title":"Fairness via Source Throtting: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory System","author":"ebrahimi","year":"2010","journal-title":"Proc 19th ACM SIGPLAN Int Conf Architectural Support for Programming Languages and Operating Systems (ASPLOS)"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736036"},{"key":"ref9","article-title":"Balancing Throughput and Fairness in SMT Processors","author":"luo","year":"2001","journal-title":"Proc IEEE Int Symp Perform Anal Syst Softw (ISPASS)"},{"key":"ref20","article-title":"Estimating Cache Misses and Locality Using Stack Distances","author":"cabcaval","year":"2003","journal-title":"Proc 17th ACM Int Conf Supercomputing (ICS)"},{"key":"ref22","doi-asserted-by":"crossref","DOI":"10.1109\/ISCA.2008.7","article-title":"Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems","author":"mutlu","year":"2008","journal-title":"Proc ACM \/IEEE 35th Int Symp Computer Architecture (ISCA)"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2004.1342546"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/1809049.1809065"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/2254756.2254792"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/1094811.1094835"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/CDC.2010.5717893"}],"container-title":["IEEE Transactions on Parallel and Distributed Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/71\/7010070\/06766707.pdf?arnumber=6766707","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:01:05Z","timestamp":1642003265000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6766707\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,2]]},"references-count":29,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tpds.2014.2306411","relation":{},"ISSN":["1045-9219","1558-2183","2161-9883"],"issn-type":[{"value":"1045-9219","type":"print"},{"value":"1558-2183","type":"electronic"},{"value":"2161-9883","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,2]]}}}