{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,26]],"date-time":"2025-09-26T13:29:30Z","timestamp":1758893370679},"reference-count":42,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2015,9,1]],"date-time":"2015-09-01T00:00:00Z","timestamp":1441065600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Parallel Distrib. Syst."],"published-print":{"date-parts":[[2015,9,1]]},"DOI":"10.1109\/tpds.2014.2351816","type":"journal-article","created":{"date-parts":[[2014,8,26]],"date-time":"2014-08-26T18:33:09Z","timestamp":1409077989000},"page":"2479-2492","source":"Crossref","is-referenced-by-count":13,"title":["Heterogeneous NoC Router Architecture"],"prefix":"10.1109","volume":"26","author":[{"given":"Yaniv","family":"Ben-Itzhak","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Israel","family":"Cidon","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Avinoam","family":"Kolodny","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael","family":"Shabun","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nir","family":"Shmuel","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1145\/1064978.1065034"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771803"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2001.903268"},{"key":"ref31","first-page":"141","article-title":"Scalable pipelined interconnect for distributed endpoint routing: The sgi spider chip","author":"galles","year":"0","journal-title":"Proc Hot Interconnects"},{"key":"ref30","article-title":"On-die interconnects for next generation cmps","author":"kundu","year":"0"},{"key":"ref37","article-title":"The OMNeT++ discrete event simulation system","author":"varga","year":"0"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/SAMOS.2012.6404157"},{"key":"ref35","author":"smith","year":"1997","journal-title":"The Scientist and Engineer's Guide to Digital Signal Processing"},{"key":"ref34","doi-asserted-by":"crossref","first-page":"188","DOI":"10.1145\/1028176.1006717","article-title":"Low-latency virtual-channel routers for on-chip networks","volume":"32","author":"mullins","year":"2004","journal-title":"ACM SIGARCH Comput Arch News"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1002\/0470113952"},{"key":"ref40","article-title":"Buffer allocation approaches for virtual channel flow control","author":"parik","year":"0"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2007.169"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837384"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2024723.2000112"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/1150343.1150365"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.50"},{"key":"ref16","first-page":"190","article-title":"Design space exploration comparing homogeneous and heterogeneous network-on-chip architectures","author":"kreutz","year":"0","journal-title":"Proc 18th Annu Symp Integr Circuits Syst Des"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2011.6105419"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2010.17"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2011.6081402"},{"key":"ref28","first-page":"63","article-title":"A 4.6 tbits\/s 3.6 ghz single-cycle noc router with a novel switch allocator in 65nm cmos","author":"kumar","year":"0","journal-title":"Proc 25th Int Conf Comput Des"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2004.21"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/500001.500009"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2005.22"},{"key":"ref6","article-title":"Survey of network on chip (NoC) architectures & contributions","volume":"3","author":"agarwal","year":"2009","journal-title":"J Eng Comput Arch"},{"key":"ref29","first-page":"333","article-title":"ViChaR: A dynamic virtual channel regulator for network-on-chip routers","author":"nicopoulos","year":"0","journal-title":"Proc 39th Annu IEEE\/ACM Int Symp Microarchit"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2006.243951"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2004.03.003"},{"key":"ref7","article-title":"Survey of network-on-chip proposals","author":"salminen","year":"0","journal-title":"White paper OCP-IP"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000111"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/2347655.2347670"},{"key":"ref1","author":"dally","year":"2004","journal-title":"Principles and Practices of Interconnection Networks"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.29"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/1531542.1531658"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147122"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2005.427"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/964725.633050"},{"key":"ref41","article-title":"Deep versus parallel buffers in wormhole switched k-ary n-cubes","author":"alzeidi","year":"0"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2011.5770788"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090700"},{"key":"ref25","first-page":"105","article-title":"Power-driven design of router microarchitectures in on-chip networks","author":"wang","year":"0","journal-title":"Proc 36th Annu IEEE\/ACM Int Symp Microarchit"}],"container-title":["IEEE Transactions on Parallel and Distributed Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/71\/7180482\/06883223.pdf?arnumber=6883223","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:41:32Z","timestamp":1642005692000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6883223\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,9,1]]},"references-count":42,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/tpds.2014.2351816","relation":{},"ISSN":["1045-9219"],"issn-type":[{"value":"1045-9219","type":"print"}],"subject":[],"published":{"date-parts":[[2015,9,1]]}}}