{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,1]],"date-time":"2026-03-01T05:07:34Z","timestamp":1772341654703,"version":"3.50.1"},"reference-count":46,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2015,11,1]],"date-time":"2015-11-01T00:00:00Z","timestamp":1446336000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/100000899","name":"Intel Collaborative Research Institute for Computational Intelligence","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100000899","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Hasso-Plattner-Institut"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Parallel Distrib. Syst."],"published-print":{"date-parts":[[2015,11,1]]},"DOI":"10.1109\/tpds.2014.2370055","type":"journal-article","created":{"date-parts":[[2014,11,12]],"date-time":"2014-11-12T19:40:13Z","timestamp":1415821213000},"page":"3175-3183","source":"Crossref","is-referenced-by-count":31,"title":["Sparse Matrix Multiplication On An Associative Processor"],"prefix":"10.1109","volume":"26","author":[{"given":"L.","family":"Yavits","sequence":"first","affiliation":[]},{"given":"A.","family":"Morad","sequence":"additional","affiliation":[]},{"given":"R.","family":"Ginosar","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2007.375263"},{"key":"ref38","article-title":"Automatic performance tuning of sparse matrix kernels","author":"vuduc","year":"2003"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/71.963416"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/12.956091"},{"key":"ref31","article-title":"Efficient sparse matrix-vector multiplication on CUDA","volume":"20","author":"bell","year":"2008"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/1654059.1654078"},{"key":"ref37","first-page":"380","article-title":"A processor array for factorization of unstructured sparse networks","author":"kieckhager","year":"1982","journal-title":"IEEE Conf on Circuits and Computers"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/2554688.2554785"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/HPEC.2013.6670336"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1016\/0743-7315(85)90033-4"},{"key":"ref10","article-title":"New microarchitecture challenges in the coming generations of CMOS process technologies (keynote address)","author":"pollack","year":"1999","journal-title":"MICRO 32"},{"key":"ref40","first-page":"97","article-title":"Scan primitives for GPU computing","author":"sengupta","year":"2007","journal-title":"Graphics Hardware"},{"key":"ref11","author":"blelloch","year":"1990","journal-title":"Vector Models for Data-Parallel Computing"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1007\/s11227-008-0251-8"},{"key":"ref13","article-title":"AP-DIMM: Associative Computing with STT-MRAM","author":"qing","year":"2013","journal-title":"ISCA"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.872719"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/12.166599"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1016\/0167-8191(92)90007-T"},{"key":"ref17","doi-asserted-by":"crossref","first-page":"917","DOI":"10.1145\/882262.882364","article-title":"Sparse matrix solvers on the GPU: Conjugate gradients and multigrid","volume":"22","author":"bolz","year":"2003","journal-title":"ACM Trans Graph"},{"key":"ref18","article-title":"SpMV: A memory-bound application on the GPU stuck between a rock and a hard place","author":"davis","year":"2012"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1201\/b10376"},{"key":"ref4","article-title":"Content Addressable Parallel Processors","author":"foster","year":"1976"},{"key":"ref28","article-title":"Optimizing sparse matrix-vector multiplication on GPUs using compile-time and run-time strategies","volume":"rc24704","author":"baskaran","year":"2008","journal-title":"IBM Research Report"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2012.6242496"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/1046192.1046202"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1016\/S0010-4655(01)00164-3"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/CMPCON.1991.128817"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1016\/0167-8191(93)90004-5"},{"key":"ref8","article-title":"Optimizing the performance of sparse matrix-vector multiplication","author":"im","year":"2000"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/EIT.2009.5189662"},{"key":"ref2","first-page":"30","article-title":"Improving performance of sparse matrix-vector multiplication","author":"pinar","year":"1999","journal-title":"Proc ACM\/IEEE Conf Supercomputing"},{"key":"ref9","first-page":"1078","article-title":"Performance evaluation of sparse matrix multiplication kernels on Intel xeon phi","volume":"1302","author":"saule","year":"2013","journal-title":"Arxiv preprint arXiv"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPSW.2013.166"},{"key":"ref46","article-title":"PSPARSLIB: A portable library of distributed memory sparse iterative solvers","author":"saad","year":"1995"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2007.56"},{"key":"ref45","doi-asserted-by":"crossref","first-page":"3","DOI":"10.1145\/356683.356685","article-title":"Associative processor architecture—a survey","volume":"9","author":"fung","year":"1977","journal-title":"ACM Comput Surv J"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.864128"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2049867"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1016\/j.parco.2008.12.006"},{"key":"ref24","article-title":"Associative Processor","author":"yavits","year":"2014","journal-title":"Supplementary Material"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1147\/rd.416.0711"},{"key":"ref23","article-title":"Architecture and design of Associative Processor for image processing and computer vision","author":"yavits","year":"1994"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1145\/2464996.2465013"},{"key":"ref26","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1016\/j.parco.2013.11.001","article-title":"The effect of communication and synchronization on Amdahl's law in multicore systems","volume":"40","author":"yavits","year":"2013","journal-title":"Parallel Comput J"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1145\/2049662.2049663"},{"key":"ref25","article-title":"Computer architecture with associative processor replacing last level cache and SIMD accelerator","author":"yavits","year":"2014","journal-title":"IEEE Trans Comput"}],"container-title":["IEEE Transactions on Parallel and Distributed Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/71\/7293777\/06954570.pdf?arnumber=6954570","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:28:19Z","timestamp":1642004899000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6954570\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,11,1]]},"references-count":46,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tpds.2014.2370055","relation":{},"ISSN":["1045-9219"],"issn-type":[{"value":"1045-9219","type":"print"}],"subject":[],"published":{"date-parts":[[2015,11,1]]}}}