{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T16:22:18Z","timestamp":1781886138203,"version":"3.54.5"},"reference-count":67,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2016,6,1]],"date-time":"2016-06-01T00:00:00Z","timestamp":1464739200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/100000015","name":"US Department of Energy","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100000015","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100006132","name":"Office of Science","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100006132","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100006192","name":"Advanced Scientific Computing Research","doi-asserted-by":"crossref","id":[{"id":"10.13039\/100006192","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Parallel Distrib. Syst."],"published-print":{"date-parts":[[2016,6,1]]},"DOI":"10.1109\/tpds.2015.2461155","type":"journal-article","created":{"date-parts":[[2015,8,13]],"date-time":"2015-08-13T11:35:54Z","timestamp":1439465754000},"page":"1852-1863","source":"Crossref","is-referenced-by-count":38,"title":["A Survey Of Techniques for Architecting DRAM Caches"],"prefix":"10.1109","volume":"27","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-2908-993X","authenticated-orcid":false,"given":"Sparsh","family":"Mittal","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jeffrey S.","family":"Vetter","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2007.4601880"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2014.2355193"},{"key":"ref33","doi-asserted-by":"crossref","first-page":"1543","DOI":"10.7873\/DATE.2015.0733","article-title":"Destiny: A Tool for Modeling Emerging 3D NVM and eDRAM Caches","author":"matt poremba","year":"2015","journal-title":"Design Automation Test in Europe Conference Exhibition (DATE)"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2012.2"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.032"},{"key":"ref30","article-title":"Challenges in heterogeneous die-stacked and off-chip memory systems","author":"loh","year":"0","journal-title":"Proc 3rd Workshop SoCs Heterogeneity Workloads"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1142\/S0218126614501473"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485958"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.31"},{"key":"ref34","article-title":"BATMAN: Maximizing bandwidth utilization of hybrid memory systems","author":"chou","year":"2015"},{"key":"ref60","doi-asserted-by":"publisher","DOI":"10.1109\/ISOCC.2012.6406899"},{"key":"ref62","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2009.11"},{"key":"ref61","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.13"},{"key":"ref63","article-title":"Design and evaluation of a subblock cache coherence protocol for bus-based multiprocessors","author":"anderson","year":"1994"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2010.50"},{"key":"ref64","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2015.2426179"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593197"},{"key":"ref65","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485960"},{"key":"ref66","article-title":"A survey of power management techniques for phase change memory","author":"mittal","year":"2014","journal-title":"Int J Comput Aided Eng Technol"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155673"},{"key":"ref67","doi-asserted-by":"publisher","DOI":"10.1145\/2503210.2503215"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2012.6378637"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757356"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2014.2324563"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/2668930.2688044"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.36"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1504\/IJHPSA.2012.050990"},{"key":"ref23","first-page":"33","article-title":"CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory","author":"chen","year":"0","journal-title":"Proc Conf Des Autom Test Eur"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1016\/j.suscom.2013.11.001"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.15"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669141"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.51"},{"key":"ref59","first-page":"1","article-title":"DRAM-based coherent caches and how to take advantage of the coherence protocol to reduce the refresh energy","author":"jaksic","year":"0","journal-title":"Proc Des Autom Test Eur Conf Exhib"},{"key":"ref58","first-page":"198","article-title":"BEAR: Techniques for mitigating bandwidth bloat in gigascale DRAM caches","author":"chou","year":"0","journal-title":"Proc 42nd Annu Int Symp Comput Archit"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2012.6271803"},{"key":"ref56","doi-asserted-by":"crossref","first-page":"554","DOI":"10.1145\/1391469.1391610","article-title":"circuit and microarchitecture evaluation of 3d stacking magnetic ram (mram) as a universal memory replacement","author":"xiangyu dong","year":"2008","journal-title":"2008 45th ACM\/IEEE Design Automation Conference DAC"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1145\/2141702.2141712"},{"key":"ref54","article-title":"Enabling efficient dynamic resizing of large DRAM caches via a hardware consistent hashing mechanism","author":"chang","year":"2013"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485957"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1145\/2628071.2628089"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.63"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2015.0710"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2009.5161016"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2010.5416642"},{"key":"ref13","first-page":"496","article-title":"A 1.2V 12.8GB\/s 2Gb mobile Wide-I\/O DRAM with 4X128 I\/Os using TSV-based stacking","author":"kim","year":"0","journal-title":"Proc IEEE Int Solid-State Circuits Conf Digest Tech Papers"},{"key":"ref14","first-page":"130","article-title":"8Gb 3D DDR3 DRAM using through-silicon-via technology","author":"kang","year":"0","journal-title":"Proc IEEE Int Solid-State Circuits Conf -Digest Tech Papers"},{"key":"ref15","year":"0"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2012.6242474"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2360379"},{"key":"ref18","year":"2015"},{"key":"ref19","year":"2014"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555801"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056027"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.18"},{"key":"ref5","article-title":"Power scaling: The ultimate obstacle to 1K-core chips","author":"hardavellas","year":"2010"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.30"},{"key":"ref7","first-page":"4009","article-title":"Exploring DRAM last level cache for 3D network-on-chip architecture","volume":"403","author":"xu","year":"2012","journal-title":"Advances in Materials Research"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798261"},{"key":"ref9","year":"2014"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/CASES.2013.6662515"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/CODES-ISSS.2013.6658988"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/Co-HPC.2014.8"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/3DIC.2013.6702397"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669139"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2009.93"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.030"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2011.6026484"}],"container-title":["IEEE Transactions on Parallel and Distributed Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/71\/7469437\/07181712.pdf?arnumber=7181712","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:48:51Z","timestamp":1641988131000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7181712\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,6,1]]},"references-count":67,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/tpds.2015.2461155","relation":{},"ISSN":["1045-9219"],"issn-type":[{"value":"1045-9219","type":"print"}],"subject":[],"published":{"date-parts":[[2016,6,1]]}}}