{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,16]],"date-time":"2025-07-16T12:14:37Z","timestamp":1752668077589,"version":"3.37.3"},"reference-count":40,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2016,9,1]],"date-time":"2016-09-01T00:00:00Z","timestamp":1472688000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100003593","name":"CNPq","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100003593","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100002322","name":"CAPES","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100002322","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Parallel Distrib. Syst."],"published-print":{"date-parts":[[2016,9,1]]},"DOI":"10.1109\/tpds.2015.2504985","type":"journal-article","created":{"date-parts":[[2015,12,3]],"date-time":"2015-12-03T19:06:17Z","timestamp":1449169577000},"page":"2653-2666","source":"Crossref","is-referenced-by-count":13,"title":["Kernel-Based Thread and Data Mapping for Improved Memory Affinity"],"prefix":"10.1109","volume":"27","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-9064-7806","authenticated-orcid":false,"given":"Matthias","family":"Diener","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Eduardo H. M.","family":"Cruz","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Marco A. Z.","family":"Alves","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Philippe O. A.","family":"Navaux","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Anselm","family":"Busse","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hans-Ulrich","family":"Heiss","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"ref38","article-title":"Lmbench: Portable tools for performance analysis","author":"mcvoy","year":"0","journal-title":"Proc USENIX Annu Tech Conf"},{"article-title":"The SGI altix 3000 Global Shared-memory architecture","year":"2005","author":"woodacre","key":"ref33"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2013.104"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/SHPCC.1994.296682"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/PDP.2015.25"},{"year":"2012","key":"ref37","article-title":"AMD opteron 6300 series processor quick reference guide"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/HOTI.2010.24"},{"year":"2010","key":"ref35","article-title":"Intel Xeon Processor 7500 Series"},{"year":"2007","key":"ref34","article-title":"Dual-core intel itanium processor 9000 and 9100 series"},{"key":"ref10","first-page":"387","article-title":"Affinity-on-next-touch: Increasing the performance of an industrial PDE solver on a cc-NUMA system","author":"l\u00f6f","year":"0","journal-title":"Proc Int Conf Supercomput"},{"year":"0","key":"ref40","article-title":"Using KMP_AFFINITY to create OpenMP thread mapping to OS proc IDs"},{"year":"2012","author":"corbet","key":"ref11"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/1854273.1854350"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2010.5470442"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2259016.2259046"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/2628071.2628077"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.2000.876083"},{"key":"ref17","first-page":"279","article-title":"Improving memory affinity of geophysics applications on NUMA platforms using Minas","author":"ribeiro","year":"0","journal-title":"Proc Int Conf High Perform Comput Comput Sci"},{"key":"ref18","doi-asserted-by":"crossref","first-page":"1204","DOI":"10.1016\/j.jpdc.2010.08.015","article-title":"Feedback-directed page placement for ccNUMA via Hardware-generated memory traces","volume":"70","author":"marathe","year":"2010","journal-title":"J Parallel Distrib Comput"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1016\/0743-7315(92)90051-N"},{"article-title":"The OpenMP implementation of NAS parallel benchmarks and its performance","year":"1999","author":"jin","key":"ref28"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1531793.1531803"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/2445572.2445577"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/SBAC-PAD.2009.16"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/2451116.2451157"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/1065010.1065034"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2628071.2628085"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/IPPS.1995.395974"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/PDP.2015.11"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2012.6189222"},{"article-title":"An NUMA API for Linux.","year":"0","author":"kleen","key":"ref9"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1854273.1854314"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/1122971.1122987"},{"key":"ref22","first-page":"198","article-title":"Optimizing memory locality using a Locality-aware page table","author":"cruz","year":"0","journal-title":"Proc Int Symp Comput Archit High Perform Comput"},{"key":"ref21","doi-asserted-by":"crossref","first-page":"1186","DOI":"10.1016\/j.jpdc.2008.05.006","article-title":"Hardware monitors for dynamic page migration","volume":"68","author":"tikir","year":"2008","journal-title":"J Parallel Distrib Comput"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2012.311"},{"key":"ref23","first-page":"1","article-title":"Autopin&#x2014;Automated optimization of thread-to-core pinning on multicore systems","author":"klug","year":"0","journal-title":"Proc Workshop Programmability Issues Multi-Core Comput"},{"article-title":"Increasing energy efficiency of processor caches via line usage predictors","year":"2014","author":"alves","key":"ref26"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2013.57"}],"container-title":["IEEE Transactions on Parallel and Distributed Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/71\/7534960\/07345593.pdf?arnumber=7345593","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T02:33:53Z","timestamp":1633919633000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7345593\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,9,1]]},"references-count":40,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/tpds.2015.2504985","relation":{},"ISSN":["1045-9219"],"issn-type":[{"type":"print","value":"1045-9219"}],"subject":[],"published":{"date-parts":[[2016,9,1]]}}}