{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:19:00Z","timestamp":1740133140460,"version":"3.37.3"},"reference-count":36,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2016,10,1]],"date-time":"2016-10-01T00:00:00Z","timestamp":1475280000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100003329","name":"Ministry of Economy and Competitiveness of Spain","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100003329","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100002924","name":"FEDER","doi-asserted-by":"publisher","award":["TIN2013-42148-P"],"award-info":[{"award-number":["TIN2013-42148-P"]}],"id":[{"id":"10.13039\/501100002924","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Parallel Distrib. Syst."],"published-print":{"date-parts":[[2016,10,1]]},"DOI":"10.1109\/tpds.2016.2516540","type":"journal-article","created":{"date-parts":[[2016,1,11]],"date-time":"2016-01-11T14:06:52Z","timestamp":1452521212000},"page":"2824-2837","source":"Crossref","is-referenced-by-count":10,"title":["Cache Line Aware Algorithm Design for Cache-Coherent Architectures"],"prefix":"10.1109","volume":"27","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-6656-9732","authenticated-orcid":false,"given":"Sabela","family":"Ramos","sequence":"first","affiliation":[]},{"given":"Torsten","family":"Hoefler","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1016\/j.jcss.2010.06.012"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/63404.63407"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1002\/cpe.3416"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/103727.103729"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/HPCSim.2014.6903790"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/2517349.2522714"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1016\/j.parco.2012.11.003"},{"year":"0","author":"volkov","key":"ref10"},{"year":"2013","author":"dolbeau","key":"ref11"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/12.286299"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2493123.2462903"},{"year":"2012","author":"ramos","key":"ref14"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2006.1639561"},{"key":"ref16","first-page":"939","article-title":"Advantages of forward thinking in generating rooted and free trees","author":"li","year":"0","journal-title":"Proc 10th ACM-SIAM Symp Discr Algorithms"},{"article-title":"Intel Xeon Phi Coprocessor Vector Microarchitecture","year":"2012","author":"rahman","key":"ref17"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/173284.155333"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/215399.215427"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/165231.165250"},{"year":"2014","key":"ref4","article-title":"Intel Xeon Phi Coprocessor: Software Developers Guide"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/1463768.1463780"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669165"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2012.86"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1016\/j.parco.2009.09.001"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/HOTCHIPS.2012.7476487"},{"key":"ref8","first-page":"97","article-title":"Modeling communication in cache-coherent SMP cystems: A case-study with Xeon Phi","author":"ramos","year":"0","journal-title":"Proc 22nd Int Symp High-Perform Parallel Distrib Comput"},{"key":"ref7","first-page":"85","article-title":"Cache line aware programming for ccNUMA systems","author":"ramos","year":"0","journal-title":"Proc Int Symp High-Perform Parallel Distrib Comput"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2009.22"},{"year":"2014","key":"ref9","article-title":"Intel 64 and IA-32 architectures optimization ref. manual"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-10214-6_2"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-45591-4_162"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2007.38"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1016\/S0167-8191(06)80021-9"},{"article-title":"A survey of parallel algorithms for shared-memory machines","year":"1988","author":"karp","key":"ref24"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2003.1213137"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/1531743.1531769"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/CCGRID.2010.60"}],"container-title":["IEEE Transactions on Parallel and Distributed Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/71\/7563479\/07378320.pdf?arnumber=7378320","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:43:29Z","timestamp":1641987809000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7378320\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,10,1]]},"references-count":36,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tpds.2016.2516540","relation":{},"ISSN":["1045-9219"],"issn-type":[{"type":"print","value":"1045-9219"}],"subject":[],"published":{"date-parts":[[2016,10,1]]}}}